FPGA loop timing and data transfer question

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Hi Community,

two really rookie question about FPGA loop timing. Attached a screenshot of the data acquision loop I have created. The different modules have different maximum sampling rates, so what will be the execution speed of the loop? Will it adjust to the slowest module, or should I use a loop timer? 

This is the acquisition loop but I need to process the data as well. Currently I transmit the data to the processor loop via that fixed length FXP array. I guess the best would be to use a FIFO. Can you confirm this? Or should I use something else?

Thanks!

[Sam_Sharp · Accepted solution]

Yes, the loop rate will be determined by the slowest module. If you have some really slow analogue input module, you might want to put that in a separate loop to your fast IO. You could always put some timing information in your loop to view your actual loop rate using a shift register, subtract and a tick count VI.

You're right - for lossless high speed data acquisition (without losing any points of data) you should use FIFOs. If you don't care about missing points of data (i.e. only interested in the current value) then reading from the front panel indicator is fine.