FPGA constant matrix times a vector using Linear Algebra Matrix Multiply

[dfjuggler]

Thanks Matt, the thing is that the configuration I've set for the high-throughput matrix multiply VI outputs a 1D array of one element. The Index Array VI is basically there to turn the 1D array into a scalar. I was hoping that the first iteration of the For Loop would make the inner SCTL ouput the first result and so on with the second.

I've explored the process a bit more and realised I wasn't passing the second row of A at the right time. To illustrate the process I created arrays with the values for different signals part of the handshaking and got this result:

It seems that one needs to input the values for A and b during iterations 0 to 2. The results come 10 cycles later, at iterations 10 and 11. It should also be noted that during iterations 5 and 6, new values for A and b are being loaded, which means those will be used to provide results at 14 and 15. Similarly with values loaded on iterations 9 and 10.

I was intending to use this code as a SubVI, so I'm not sure it would work as is. It feels like I should be doing a cleverer management of the handshaking signals. For the time being, for this particular application I'll be using the Matrix*Vector block from the FPGA Math & Analysis >> Control palette. I've still got some studying to do regarding high-throughput VIs.

Thanks!

[MrQuestion]

From experience I caution the use of SCTL within a subVI. 

It is very possible that you will experience clock domain issues, and get compile errors.

Unless you intened to use some type of shared memory exchange, or FIFO where this is technically no longer a "subVI" but a parallel process. (FPGA's are good at this)

As soon as I get my home license going again I can create some sample code that will demonstrate the usage of the feedback nodes.

(I wonder when NI will get completly on the cloud bandwagon where I can just log onto NI and use the full version of LabVIEW.)

The "ready for A", and "ready for B" outputs are important feedback indicators. 

Without feeding back these outputs in the next iteration there is no way of telling where you are in the processing pipe. If you know the configuration of the IP (such as how long the processing pipe will be) you might be able to get away without using feedback, but it is more complicated.

Also, the "output valid" output is is used to literally tell you when the output is valid. 

Look at this Pipelining to Optimize FPGA

The matrix VI that you are using utilizes pipelining. As you can see from the diagrams on that page any data that you get out of this Matrix VI is junk unless this "output valid" is high.

-good luck