FPGA block RAM access protection?

[ErikL68]

Does LabVIEW FPGA put any type of protection around accessing block RAM (BRAM)?  In other words, if I have the same BRAM accessed from multiple loops in the FPGA, some reading, some writing, some in the same loop possibly writing to different addresses simultaneously (at least, in the dataflow they appear simultaneous), does LabVIEW use anything like a semaphore to limit access to one at a time?  I don't see the benefit of using FIFOs over BRAM either, as these loops run at wildly different rates (some update memory, others pull memory to write to I/O).

If not, what is the best method to implement such protection on the FPGA?

I saw an example of a Semaphore using a single-element VI-defined boolean FIFO in a reentrant sub-VI, presumably implemented in flip-flops (implementation options being a LV 2012 addition?).

I'm using 94% of my slices in the sbRIO-9636 right now, so I'd hate to have a bunch of semaphores wasting resources if they're not needed.

Also:  I've defined numerous separate BRAMs.  Does it make sense to have separate Semaphores, or is the entirety of the BRAM accessed using the same address lines, making a single Semaphore the only way to protect them?

Thanks,

Erik

[Aix-La-Chapelle · Accepted solution]

Hi Erik,

BRAM is protected.  I believe you are referring to this white paper on our website: http://zone.ni.com/devzone/cda/epd/p/id/6014

It protected as per this statement: "For most shared resources in LabVIEW FPGA this is handled automatically and the code is added during the code generation process."

Thanks!

[MrQuestion]

I have not created a cRIO project before, but I have developed several FlexRIO FPGA projects.

LabVIEW allows you to share resources easily, but for many resources it will implement an auto arbitration algorithm. This is nice when you just want to dump data somewhere and don't care about time. However, you mentioned that you have multiple reads and multiple writes going on in parallel.

I don't know the nature of your software, but you might get into some chase issues if you try reading a block of data that hasn't bee written to already.

When I need to use a shared resource, i use my own arbitration schema. This allows me more control over the time and sequencing who wants to access the resource.

I know that in the LabVIEW examples for FlexRIO there is an example showing a memory manager for accessing external RAM. I used that concept for several other shared resource schemas.

I hope that helps.