FPGA Xilinx Error Using CLIP, Xilinx Bug?

[jakidd]

I get the following errors when compiling FPGA using CLIP. According to Xilinx this is a known bug (30477) in 10.1. Can I upgrade the Xilinx compiler somehow, or is there a workaround? The CLIP works fine if I drop it into LabView FPGA, but when I add LabView code around it the errors occur.

ERROR:MapLib:979 - LUT5 symbol
   "Puma15Window/theVI/n_00000014/nSCTL_0000002C_0000002D/n_00000159/n_0000009B/
   n_000000B8/Mmux_sel00000055_t00000001_6" (output
   signal=Puma15Window/theVI/n_00000014/nSCTL_0000002C_0000002D/n_00000159/n_000
   0009B/n_000000B8/Mmux_sel00000055_t00000001_6) has input signal
   "Puma15Window/theVI/Component_Level_IP_Command_Complete_din/cSecondRegister<0
   >" which will be trimmed. See Section 5 of the Map Report File for details
   about why the input signal will become undriven.

 ERROR:MapLib:978 - LUT5 symbol
   "Puma15Window/theVI/n_00000014/nSCTL_0000002C_0000002D/n_00000159/n_0000009B/
   n_000000B8/Mmux_sel00000055_t00000001_6" (output
   signal=Puma15Window/theVI/n_00000014/nSCTL_0000002C_0000002D/n_00000159/n_000
   0009B/n_000000B8/Mmux_sel00000055_t00000001_6) has an equation that uses
   input pin I0, which no longer has a connected signal. Please ensure that all
   the pins used in the equation for this LUT have signals that are not trimmed
   (see Section 5 of the Map Report File for details on which signals were
   trimmed).

http://www.xilinx.com/support/answers/30477.htm

Xilinx 10.1 known issues - 30477

Using version LabView/FPGA 2009

Message Edited by jakidd on 10-02-2009 03:20 PM

[Ben_S]

jakidd,

As this is a Xilinx Compiler error and the workarounds listed on the Xilinx website are for options we can't access from LabVIEW FPGA there may not be a solution for this issue. Could you attach a working VI and a VI with the minimal amout of code that causes this error?

A possible workaround would be for you to try and compile your code in LabVIEW 8.6.1 as it uses an older Xilinx compliler.

[RyanB]

Are you instantiating multiple ICON/ILA cores as mentioned in the answer record?  I assume you are using these to debug via Chipscope.  Can you instantiate one at a time?

-RB

[StephenD]

Check to make sure that all of your VHDL components have a path in the implementation list tag of the XML file.  If any VHDL component or subcomponent  are missing, Xilinx will instantiate a block box in synthesis and not error, trim the signals, and then later cause possible mapping errors like the ones posted.