FPGA Using VHDL IP and an Analog output

[APLUserX]

I'm using a PXI System with Labview 2014. I've got Labview FPGA installed to program and run the PXI-7854R Card.

I have VHDL Code that I would like to use to drive an analog output from the Card. I'm using the IP Integration Node for this currently however I've also tried this doing the CLIP process and still haven't had success. The problem that arises is that the IP Integration Node has to be within a timed loop while the Analog output states that it cannot be put into a timed loop. Is there any way to provide an output from VHDL to the Analog outputs of the Card?

I've attempted to nest a timed loop within a while loop but it still doesn't work.

I cannot upload the VI's due to company policy, but assume that I am generating a sine wave in my VHDL code that needs to drive the analog output of Card (The actual wave is proprietary company information but it is generated via a look up table much like a VHDL sine wave would be).

[David-A]

I'm surprised that putting the IPIN into a timed loop that was inside of a while loop didn't work.

If your confident thats not working you can try running the IPIN in a timed loop and then use a FIFO to cross clock domains into the while loop where you can pull data out of the fifo and wire it up to the AO node. You'll want to create some logic in the timed loop that monitors the FIFO to see when it is full and pauses the waveform generation of the IPIN. You'll need this since the timed loop will likely be running much faster than the while loop.

[Kelle]

Is it possible to put your VHDL code and the analog output in different loops and pass your information from one loop to the other using fifo?

-- seems like I'm a bit late to the reply, as David has suggested the same thing above

[APLUserX · Accepted solution]

In an attempt work the problem I retried the CLIP import of HDL code in a fresh Labview Project and VI. I'm still unsure as to why it wasn't working with the other one when I tried it.

For anyone else looking to solve this issue:

I essentially used this tutorial for the CLIP Process: http://www.ni.com/tutorial/7444/en/

It also explains the differences between the CLIP and IP Integration Node.