Re : FPGA: Timing Error

[kwalker]

Hello all,

I have a problem with the compiler for FPGA. When I try to compile the attached VI it gives me a timing error, which i cannot figure out. When compiled on a different Computer, however, it works fine. The latest critical updates are all installed but the error message was he same without the updates.

Any help would be highly appreciated!

Regards,

kwalker

[Sam_Sharp]

Do you have the same versions of LabVIEW, FPGA Toolkit, Xilinx Tools and CompactRIO/RIO drivers installed on both machines? Are you compiling the VI using the same LabVIEW project/target/build specification?

You could also try changing the compiler optimisation settings, copying+pasting the code into a new VI and recompiling.

[bcl511 · Accepted solution]

Hi,

On the system that fails with the timing error - what is the margin of error?  That is, what is the difference between the maximum clock rate that the tools say your design could run at and the specified clock rate?  If it is just barely failing on the one, then it is likely just barely passing on the other and this might be an indication that your design is marginal in terms of timing.  If that is the case, you could try pipelining the logic in your SCTLs to see if the timing error goes away.  For instance, it looks like you could safely put a feedback node between the greater than block and the last selector block without changing the behavior of your algo (just adding 1 cycle of latency).  

Regards,

bcl511

[kwalker]

Thanks a lot! Pipelining did the trick.

I guess, this was just a minor issue but being relatively new to Labview i find it hard to figure out these sorts of things myself.

Anyway, thanks for the replies!

Cheers,

kwalker