08-05-2012 09:41 AM
I am using Labview 2011 with an FPGA PCI card- 7833R.
My problem is that whenever I try to incorporate FPGA designed VIs into my code, I get a timing error. See pictures posted below.
In this case, I have a PID express VI which I use in a regular while loop (not even timed!) in my FPGA code, but upon compilation I get an error saying that the maximum clockrate possible is 43 MHz.
I have many loops, some run on 80 MHz. Is there a way to slow down a specific while loop, so that it runs at 40 MHz and not 80 MHz like the other? The compiler doesn't seem to respond to simply adding a loop timer...
P.S. The same thing happens when I try to add a low-pass filter VI to the FPGA code.
Solved! Go to Solution.
08-07-2012 02:59 PM
What do you have the Sample Time of the PID Express VI set to?
Have you tried using a Timed Loop Structure with the 40MHz OnBoard clock as its source?
Are you certain this error is a result of this loop? If you were to compile an FPGA project with just this segment of code in the project, does this error still occur?
Let me know, and I'll see what else I can find for you.
08-08-2012 01:34 AM
Thanks for your reply.
As far as I know, the Sampling Time (Ts) input of the PID Express VI has nothing to do with the execution clockrate. It affect the output of the VI. Nonetheless, I've tried them all- 80 MHz, 40 MHz, and even slower clockrates.
I've also tried the Timed Loop Structure with the 40 MHz OnBoard clock as you suggested, but upon generation of the compilation files it tells me that this object (PID Express VI) is not supported in the single-cycle Timed Loop. This is also true for the Tick Count Express VI and the Filter VI.
I'm certain this error is a result of this loop, as I've tried to compile an FPGA VI which includes just this loop and nothing else.
Is this some sort of bug? Or perhaps I have the FPGA or compiler inefficiently configured somehow?
Again, thanks for your time.
P.S. I'm attaching the project window, showing the configuration of my FPGA.
08-08-2012 03:39 PM
I'm going to set up the hardware and try compiling the code here on the same hardware to see if I can reproduce the issue. It shouldn't take too long once I track down all of the hardware.
Let me know if there are any remaining details I should know before I get started!
08-09-2012 02:09 AM
I guess the main issue is about FPGA clockrate and how to manage it. I think these VIs would work at 40 MHz, but I also need the 80 MHz derived clock.
I thought that setting the rate of a regular while loop to be 40 MHz should solve the problem, but I guess I was wrong... Maybe I should try doing it with a constant and not a control variable.
08-09-2012 11:06 AM
Is it possible you set the top-level clock to 80Mhz? That's what it looks like to me. In the project explorer, right-click the FPGA target, select properties, then go to the "Top-Level Clock" category.
08-09-2012 06:17 PM
I agree with Nathan. Double check that your toplevel clock isn't set to 80MHz.
I tested it out and it only failed timing requirements with the top level clock was 80MHz as opposed to 40MHz.
08-10-2012 06:45 AM
08-10-2012 02:05 PM
If you need to specify which clock to use, use a timed while loop instead of a standard one.
Quick introduction to FPGA clocks, ignore if you already know all this:
A standard LabVIEW while loop will not necessarily execute in a single FPGA clock cycle. To guarantee that a loop will execute in a single clock cycle, use a Single-Cycle Timed Loop (SCTL) - a timed loop that uses the internal clock (or a derived clock) as the timing source. You will see SCTLs mentioned in the FPGA documentation. Code inside a SCTL uses fewer FPGA resources, but is also subject to some restrictions. You cannot place more code inside a SCTL than can execute in a single clock cycle, and some functions cannot be placed inside a SCTL because they require multiple clock cycles to execute.
In the case of the PID function, there must be something inside it that needs to execute in a single cycle and requires more time to execute than an 80mhz clock allows. Since a standard while loop is governed by the top-level clock, anything inside it that must execute in a single cycle is subject to that top-level clock even if the overall loop takes more than one cycle to execute.
08-12-2012 06:04 AM
Your post was most helpful. I'm familiar with the Single-Cycle Timed Loop structure, but I still don't understand if changing the top-level clock changes the tick count of the FPGA. I mainly use regular while loops timed using ticks.
I would think that each tick would now stand for one 40 MHz cycle (which is 25 ns). Is that correct?