FPGA Timing Error That Isnt

[DGrayEOS]

I ran into a weird timing error today. I supposedly have a timing violation, but it is of zero time. Here is the screenshot. Any ideas?

I am compiling at 120MHz, as you can see from the 8.33ns requirement above.

[Jacobson-ni]

That is really strange, would you be able to attach the code that produces this error?

[stockson]

The Xilinx log would also be helpful.

[DGrayEOS]

Unfortunately, the code is proprietary, or I would have posted it in the first place. I did keep the Xylinx log, but that, also, has a bit too much info in it. The original post was more of a fishing expedition to see if anyone else had ever seen the issue than a solution. I simply hit the recompile and got a good image the next time. I would be happy to open a service request and pursue this under NDA, since I have about a 50% success rate compiling this code.

[Intaris]

Check the log to see if the timings not met are setup and hold timings. They are not going to show up in your report.