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FPGA Timekeeper

How the FPGA Timekeeper can provide an offset from time reference in nanoseconde if the tick in the FPGA board is 25ns  @40MHz ?!

 

 

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Hello Lunik,

 

That is actually expected behavior. The FPGA timekeeper doesn't actually adjust the FPGA clock, it just uses an internal counter that is continually adjusting how much each clock tick "counts" in terms of nanoseconds.

 

For example with a 40 MHz clock, one tick is normally valued at 25 ns. So every clock tick we increment the timer forward 25 nanoseconds, and track time that way.

Well in reality the clock is not exactly 40 Mhz and each tick might really be 24.8 ns long. Inside the FPGA timekeeper then might increment 25 ns every cycle, but then every 5th cycle it would only increment 24 ns.

Not only is the clock not exactly 40 Mhz but it is moving around so the Timekeeper actually is continually changing how many cycles get incremented at 25 ns before one is incremented 24, or 26 ns.

 

Best regards.

Sabri JATLAOUI - Certified LabVIEW Architect - Certified LabVIEW Developer
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