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We appreciate your patience as we improve our online experience.
04-15-2014 08:18 AM
Whenever I try to use a Timed Loop in LabVIEW FPGA, it doesn't give me the normal options to set the "dt" instance. It works fine when I'm using timed loops on a Host VI, but not on the FPGA Target side.
This is what I see:
It shows the default clock as expected, but whenever I try to set another property, the only one available is the error:
Does anyone know how to set the "dt" timing parameter for a loop like this? Thanks in advance! 🙂
Solved! Go to Solution.
04-15-2014 08:26 AM
04-15-2014 08:29 AM
Where can the SCTL be found? This is the only timed structure I can find anywhere on the pallette. (If its not clear enough, I'm quite new to FPGA. I also am in the process of transitioning to 2013 from 2009 so its a bit different 😛 )
04-15-2014 08:32 AM - edited 04-15-2014 08:33 AM
Hi Asthma,
the SCTL (on FPGA) looks like the TWL (on PC/Realtime), we are talking about the very same structure.
BUT: on the FPGA that loop behaves different than you are used to from PC/RT!
Read the help!
Go through FPGA basics found here (basics, paragraph 6)…
04-15-2014 08:42 AM
That video was quite informative. Perhaps I have the wrong structure in mind then. My goal is to repeat a loop, say 10000 times at exactly 2 kHz. What would be the best approach to make this happen on the FPGA?
04-15-2014 08:44 AM - edited 04-15-2014 08:45 AM
04-15-2014 08:45 AM
Will do! Thank you for the help and sorry for the confusion. FPGA is quite a bit different than traditional LabVIEW on Windows.