LabVIEW
FPGA Tidbit: More flexible testing of DMA Inputs / Outputs
Whenever I need to test some FPGA code, I tend to write debug VIs which include user interface items so that I can do some interactive testing in simulation mode (where timing violations are no problem 🙂 ). Whenever I have a DMA as a main input for my code, this option has proven unwieldly. I would end up copying the majority of my FPGA code into a new VI, replacing the DMA input (or output) with whatever custom code I wanted to use for testing. This often led to problems when I had finished debugging in simulation mode, having to copy the code back and re-link with the DMAs. That was until I recently realised something.
Instead of hard-wiring a DMA Input (Host to Target) or DMA Output (Target to Host) into your main FPGA code, wire up an appropriate FIFO Control instead. Put a control for the FIFO on your FP and set it to only include the Read or Write interfaces as required. You can richt-click the left-top terminal of the DMA Read ior Write and simply choose "Create Control" to have it set with the correct parameters.
Then, in a wrapper top-level VI you can simply wire in the DMA (which is hard-coded into your project) and things work as usual. The benefit is that you can now actually wire in a normal FIFO woth both Read and Write ports and use whatever UI elements you like to fill the FIFIO with data. The sub-VI containing all the FPGA logic IS THE SAME. There is no longer any copying between production versions and debug versions of essentially the same code.
The same can be done for Target to Host DMAs, just make sure to set the Read and Write options of the controls accordingly.
If resources allow, you might even be able to compile the Debug version and do some testing directly on hardware. My Debug UIs contain over 100 controls. Each command being sent then packs the data into a common format (U64 in my case) which is then unpacked in the FPGA core for usage. As such, my UI in simulation mode also takes care of ensuring that the packing / unapacking of the parameters for DMA transfer is being performed correctly.
