FPGA PCIe-1473R Frame Grabber Basler spl8192 70km Camera

[antonialichtenegger]

Hi,

I am totally new to FPGA programming. I am using a PCIe 1473R with a Basler spl8192 70km camera. I am now trying to get images from the camera over my FPGA Frame Grabber. For that I opened the existing 1-Tab 10 Bit Camera with Frame Trigger example from Labview and added my FPGA device. Then I tried to complied the file. First it took hours so I cancelled the process and now I am getting an error saying ''Add a Read function on the block diagram for this FIFO''. Maybe someone can help me with this issue. I attached my changed VI files.

Another thing I am not sure about is, that I can see my frame grabber in the NI-MAX device list but my camera is not showing up at all?

Thank you very much in advance.

Kind regards

Antonia

[JGoebel]

Hi Antoina,

first of all, it is normal, that you don't see your camera in MAX, since its connected to the FPGA. So you will need to load a bitfile to access the camera. MAX actually could load something like a default bitfile to detect and display the camera, but it doesnt, because except for the first time you use the grabber, there will propably be a bitfile loadet wich normally shouldn't be overwritten by some standart MAX-Stuff.

About your error: Where exactly do you see this error? While running the VI? During compiling in the log-window, or before compiling the VI?

Best regards,

Jan Göbel

Applications Engineer

[berkinorbi]

Hi Antonia,

The error you're getting with the FIFO is due to the wrong configuration of the FIFO. In the example project, the FIFO is configured as a Target to Host DMA (which you use to stream data from the FPGA to your host application). In your project it is configured as a Target Scoped FIFO (which is an internal FIFO within the FPGA that you use to stream data between loops). This obviously needs at least one writer and one reader node in your FPGA VI's block diagram. Since this FIFO is supposed to be a DMA FIFO, you only have a writer node in your FPGA VI's block diagram (since the reader is in your Host VI).

I also noticed that some of the while loops don't have anything connected to their condition terminal in your FPGA code, but the run arrow is not broken somehow. I'm not sure what this means 😕

I hope this helps,

Norbert

[Mathis_B]

Regarding your FPGA compile time: I'm afraid that's normal. You have a pretty big FPGA with some fairly intricate and complex code running on there (concerning your FPGA negotiating communication and reading out a camera is not exactly a stroll through the park), which means optimising the code to make it fit onto the FPGA as well as adhere to the timing targets takes time.

On the even bigger FlexRIO cards you can easily get compilation times of 8+ hours for mildly complex code. Make sure you test as much as possible in simulation mode and only build when you are confident that you haven't made a silly mistake which causes another compilation.

Best Regards

Mathis

[antonialichtenegger]

Hi,

Thank you very much for all this useful tips, I contacted now NI support and started to change some parts of the FPGA Code. The compilation is now running and I am also compiling now over the NI cloud server it takes now only half an hour and is working. But I am still getting an error which occurs at the FIFO read function and says:

''The transfer did not complete within the timeout period or within the specified number of retries.''

I also attached my new code, maybe you could also help me further with that error?

Thank you very much in advance.

Kind regards

Antonia Lichtenegger

[antonialichtenegger]

Hi,

I further changed my VI with the help of National Instrument support, now I am getting a straight line of 0 as a image.

But I expect to get  intensity values in the waveform graph, at least some background noise.

I attached my new VIs. Maybe someone had a similar problem and could give me some ideas which things could cause my problem?

Thank you very much.

Kind regards

Antonia