FPGA Oversampling

[Joachim082]

Hi,

I am acquiring data from a laser on my FPGA via the 9871 module. The laser sends 512 packages in 500ms. Because I need a common multiple in my timing 12 packages have to be deleted. Deleted means to read the data from the serial port but not to write in my DMA fifo. I have already tried to measure the time between the packages to determine the deletion of every x package but the dma fifo is growing.

I think the only correct solution for this problem is to eliminate the data on the FPGA.

Can anybody give me a hint?

Best Regards,

-- 

Joachim

[jtagg]

Hey Joachim,

 why can't you simply send all 512 packages on to the RT host? It's not like we're talking about that much data after all. You can always decide to read 512 values on the RT side and only use 500 if you really need to.

You could also, like you said, simply not write it to the FIFO at all.

I may not understand what you want though. Could you explain a little more what needs to be done with the data from the laser?

Regards,

[Joachim082]

Joseph,

I get 512 packages in one second. Because I have to handle a dt of 2ms (one timestamp also for ai and di channels) I only need 500 packages in my continious time frame. Ok, I would not write it to the fifo. But I have to read it anywhere from the serial port. Therefore when I calc 512/12 --> every 42.66667 (divisor) package has to be deleted. How to do such decision on a fpga? I've attached an example where the divisor is 43. Therefore I will still get an fifo overflow because of the 0.666667. Therfore I have to delete in the first run every 42., second run 43., third run 43. package.

Regards,

--
Joachim

[jtagg]

I see how your logic can get a little complicated there. How about this:

make a counter that goes up to 512 and increments with every piece of data and wraps back to 0. Make an array with the position of the 12 samples you want to discard and in the main loop check the main counter to see if it is one on the list. If it is, then discard it.

You could also discard every 42nd sample until you've discarded 12 on one run of the 512 counter, then stop until it starts again.

This way you only deal with integers and counters are easy to make and very effective fpga constructs.

Hope this helps.

Regards,