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FPGA : Multiply Adder IPCore latency

Hi there,

 

I'm using a set of Xilinx IPCores in my design and have been switching some high throughput add and multiply primitives over to the equivalent DSP-based IPCore MultAdd code and have a question I can't find an answer to on the web.

 

I have my core set up as follows:

Multadd.png

 

I don't quite understand the reason for the exact latencies being displayed.

If I set A to unsigned, the Latency is 4 and 3.  If I set A to Signed it is (AB and C) 3 and 2.

I don't get this difference.  I thought the DSPs were capable of handling 25x8 Multiplications and 48 bit adds in a single step.  Why does switching between signed and unsigned for 25 bit lead to a difference in latency.  If I set the bit width of A to 24, both signed and unsigned require 3 and 2 clock cycles to complete.

 

Can anyone explain this to me?  Am I using one or two DSPs for this?

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I don't have any specific knowledge here, but from your description, it sounds like their idea of "signed" and "unsigned" is that signed adds an additional sign bit, such that making your 25-bit A a signed value means it's actually 26 bits. That would be a weird and unusual way of definining it, but it is consistent with the observation that making A 24 bits reduces the latency.

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According to datasheet ( http://www.xilinx.com/support/documentation/ip_documentation/xbip_multadd_ds717.pdf  ) you get AB = 3 and C = 2 in single DSP slice implementation (page 5). So, if you get more, implementation is probably switched internally to multiple DSPs (page 6).

Notice that all the DSP48  specifications say that they have two's complement multipliers - which are signed. Lets take Spartan-6 and DSP48A1 for example: http://www.xilinx.com/support/documentation/user_guides/ug389.pdf , page 6: "18-bit x 18-bit, two’s-complement multiplier". If you're using unsigned type, you're actually using one more bit which is normally sign bit (so single DPS is doing fine with 17-bit x17-bit unsigned inputs, or 18-bit signed x 17-bit unsigned).

For comparison, DSP48E1 on Virtex-7 and Kintex-7 ( http://www.xilinx.com/support/documentation/user_guides/ug479_7Series_DSP48E1.pdf , page 9) and DSP48E on Virtex-5 (http://www.xilinx.com/technology/dsp/xtremedsp.htm#v5 ) have "25 × 18 two’s-complement multiplier". I assume you're using one of those, as your signed configuration have AB=3 and C=2, so - going back to the beggining of this post - you're fitting in one DSP slice. When you switch to unsigned, you're over the DSP multiplying capabilities.

As for the DSP usage for unsigned configuration, I'd wager you're using 2 DSPs for multiplication and 1 more for addition. You can try to configure Multiplier and Adder Subtracter cores to see how many resources they use, and their sum should tell you about your Multiply Adder.

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Thanks PiDi for an explanation that makes a lot more sense than what I wrote. Rereading it now I see that what I wrote was totally backwards.

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OK, so that means I'm using two cascaded DSPs for what I thought would only require a single DSP.

 

Well that would explain it actually, the DSP treating the unsigned version as a 26-bit signed value and ignoring the sign so to speak.

 

Good thing I'm not short on DSP resources.....

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