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FPGA: How can I ensure that I may use the same vi in RT across projects when the FPGA design changes but the FPGA indicators/controls which the vi accesses don't change?

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Hi. I have a VI that accepts an FPGA reference as an input.  The FPGA performs several functions, but this VI only cares about one specific function and thus only accesses three of the FPGA's controls and indicators.

 

However, when I change an unrelated part of the FPGA which may add or remove or change unrelated controls and indicators, this VI breaks as it wants me to update the FPGA reference input.  

 

Is there any way to prevent this from happening (e.g. that the VI could look-up (by name) the FPGA controls that it accesses)?

 

Any help will be appreciated.

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Message 1 of 11
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Hi Anthon,

 

use a typedefined control for your FPGA reference in all the places you want to use the FPGA reference.

Then set the "bind reference" option in the FPGA Open configuration dialog to use your typedef!

Best regards,
GerdW


using LV2016/2019/2021 on Win10/11+cRIO, TestStand2016/2019
Message 2 of 11
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Thanks GerdW, however could you confirm that it will still work in this case:  

 

Say the RT vi testRT.vi accesses FPGA indicator Value1 and FPGA control Value2.  I want to give testRT.vi to other developers (via our subversion repository) and they will be using it with their own FPGA designs (all of which MUST have an indicator Value1 and control Value2).

 

Thus I want to use the same testRT.vi across different projects.  Each project would have a different and unique FPGA design (and corresponding bitfile/vi) and thus the total set of controls and indicators for each FPGA design would be different. However each FPGA design would include the controls and indicators that the testRT.vi needs.

The problem with the typedef option is that each FPGA design would require its own unique typedef and this would mean that each project would need a unique testRT.vi (far from ideal for the source controlled testRT.vi). 

 

Any ideas?

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Message 3 of 11
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Hi Anthon,

 

The problem with the typedef option is that each FPGA design would require its own unique typedef

No, I use the very same typedef reference for all my FPGA projects…

Best regards,
GerdW


using LV2016/2019/2021 on Win10/11+cRIO, TestStand2016/2019
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Ah ok but when it asks to overwrite the typedef when you select a new FPGA vi, it doesn't let you pass until you select 'Overwrite'.  This will then break all the references in the existing projects not so?

overwrite.jpg

edit: I see it doesn't break the other references but it does an automatic type case (red dot)in the calling fuction of testRT.vi.  I'll have to test this to see what the behaviour is.  Is this how you also use yours?

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Message 5 of 11
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I just overwrite the typedef - it's kind of place-holder…

(And I don't work on two or more FPGA projects at the same time.)

Best regards,
GerdW


using LV2016/2019/2021 on Win10/11+cRIO, TestStand2016/2019
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Solution
Accepted by topic author AnthonV

This is exactly what dynamic FPGA references are for. Rather than linking the FPGA reference to a particular bitfile, a dynamic reference defines a list of controls, indicators, FIFOs, etc that the bitfile must support. It's fine if there are additional elements, those will be ignored.

 

You also have the option, when using a non-dynamic FPGA reference, of configuring the reference as an indicator and removing all elements except the ones needed by your subVI, although I've never used that option.

 

Finally, if you're using multiple FPGA VIs that share some sort of functionality but not the names of the controls, you might be interested in the FPGA Advanced Session Resources.

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Thanks Nathan, be gentle as this is my first time with Dynamic FPGA refs:  for full generalisation does the attached image sum it up correctly or am I making too many assumptions about Dynamic FGPA refs' utility.

Dynamic FPGA refs.png

 

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Note - the image above has not been executed on a target so there might be run-time errors.  It is for illustration and clarification only at this time.

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Message 9 of 11
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Solution
Accepted by topic author AnthonV

That looks about right to me. Another option (not necessarily better, depends on how you're using the FPGA VI reference) is to create an indicator for the FPGA Dynamic reference by right-clicking the output from Open FPGA VI Reference; that will get you an a reference with all the controls etc populated from your VI. Make that a type definition and pass that around instead of the empty reference; that way you don't need to do the cast in every VI, and you can still wire that same reference to the subVIs that only needs a subset of the controls (for those subVIs, don't use the type definition of course, use a dynamic reference that has only the controls it needs defined).

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