FPGA Express PID vs Custom PID behaves differently ? whats is wrong

[askay]

Hello all,

I am trying to use labview FPGA Express VI in my application with cRIO 9022. I write a custom PID and compare the result of it with the express PID from FPGA palette.

It seems like integral action on express PID is too large. 

I am trying to use PID as a simple integrator providing zero proportional and derivative gain, and Ki=1. Providing an error signal of 0,1 and sampling time of 1/5000, after 10sec the integrator should build up 1. While custom one reach it apprx. 10 sec, the express VI rapidly increases up to saturation. 

What is wrong with my VI, I am sure I am missing someting. The reason why I want to use express is that it consume less space and I have to use 5 parallel PID which I cannot achieve with custom one, since it is not efficiently written. I attach the VI and png for your view.

Thank you all,

Des.

[nathand]

I can't open your code - Windows says the ZIP is invalid. Have you looked at the documentation for the FPGA PID? The gains are "normalized" - the I value you are entering is not the standard integral gain or integral time. How do you know your algorithm matches the implementation of the Express version? One reason the Express version is probably more efficient than your version is that it assumes pre-computation of the gains in the optimal form for the computation. When you use the Express VI configuration dialog, it will do this normalization for you, but when you wire in the gains, you need to do it yourself.

[askay]

Hello Nathan,

thank you for your response, I have already went through all the details. The help doc. says that if gains are wired into the express VI (entring without dialog box), it is assumed that gains are already normalized, According to help,  e(k)*[Kp + Ki + Kd], it is a parallel type.  then I just wire integral gain of 1, then rest is zero. I ve just wanted to see if  this behaves like an integrator. However it is not. I am sure there is something wrong, but I cant get to find my mistake. 

I attached the code again.

Thank you again.

[nathand · Accepted solution]

Well, the ZIP file is valid, but I'm on an older version of LabVIEW so I still can't open your VIs, sorry.

I would check your math. The help for the FPGA Express VI is clear about how the calculation works. It does not take the sample time into account - that's one of the reasons the gains are normalized. The way you have your code configured, the integrated error - and therefore the output - will increase by 0.1 for every loop iteration, regardless of the loop rate - so it will take 100 iterations for the output to reach 10. You need to adjust your integral gain to account for the actual loop cycle time.

[askay]

Hello Nathand,

Thank you again, for your help.

Considering the normalized gain has to scaled with sample time (Ts=1/5kHz), an integral gain of 1*Ts will be lower than the available resolution of the express VI, i.e. 8 Bits.

This will make my plant unstable for sure. I have just seen your post about it, that you proposed a custom one, or scaling-normalizing of the PID I/O s. 

Can you comment more on the normalization case  that you proposed?

https://forums.ni.com/t5/LabVIEW/fpga-pid-limited-by-8bits-resolution/td-p/1843107

I think I should stick on the custom math although it takes %12 DSP48s for each PID.

Thank you 

[askay]

Hi again Nathand,

I have just seen that You had already mentioned the solution here,

http://forums.ni.com/t5/LabVIEW/Synchronizing-multiple-FPGA-PID-loops/td-p/2889072

I have scaled the output and PID gains and now I have similar results with the custom one. I think  the fraction presicion of the express PID gains should be increased by NI

Thank you.