FPGA - DMA with multiple cMoudules

[anvas]

Hi!

I have a setup with a cRIO (Chassis cRIO-9114, controller cRIO-9025) and four cModules, NI 9225, NI 9227, NI 9232 and NI 9239. The NI 9232 has a max sampling rate of 102.400 kS/s while the other three have 50 kS/s.

I am using DMA FIFO to transfer the data from the FPGA and there are only three DMA channels available. Since the NI 9232 has a higher sampling rate, I have used one DMA FIFO for data transfer from this module. But for the remaining cModules, I would like transfer data from all of them in some cases while in other cases I am only interested in data from one of them. Is it a good practice to transfer all of them in one DMA FIFO? Is it possible to use one DMA FIFO to transfer data for all four cModules? 

Thanks!

[Thoric · Accepted solution]

If you transfer that much data to the RealTime code you need to be sure you can handle the processing of it, that will be a lot of data to receive, process, store/transmit etc.

But in any case, it is certainly sensible to use one DMA for the 9232 data. For the other three modules, if you are only in interested in a select number of modules each time you read from them, then you need to implement a strategy for receiving the data through a second DMA channel.

One option might be to precede the data with a single value, also sent through the secondary DMA, that defines the incoming data. For example, you might use a bit-packed byte (upconverted to whatever datatype you are passing through the DMA), within which the first three bits declare which modules are actively being read. So for 00000111 you are reading from all modules, with 00000101 you are reading from modules 1 and 3. The amount of data following this bit-packed byte will entirely depend on the modules you are reading from, clearly the maximum count will be for all three modules, but in all cases you can work this out and prepare to receive the data on the RealTime end appropriately.

This is just one suggestion. There are better options, which include packet leaders and terminators, whereby you precede the bit-packed byte with a known value to provide reassurances that the DMA buffer is still syncronised, but these concepts are harder to describe in a single thread post...