FPGA Compile Error - Xilinx Error

[Matthew_Kelton]

I am trying to compile my FPGA VI on my laptop, and have been unsuccessful in doing so.  The VI compiles fine on my lab PC.  I have tried uninstalling and reinstalling LabVIEW FPGA and Xilinx tools with no change.

I am running 2014 SP1.

I have attached my log file for the compilation.  I have tried to geenrate a new build specification with no change.  Compiling a blank VI works fine.

The FPGA VI has a couple of registers and interacts with the DIO card in FPGA mode.

I appreciate any help.

Matthew

[j_bou]

Hello Matthew_Kelton,

It is interesting that this FPGA VI will compile on your lab PC but not on your laptop. Are they running the exact same software set? Namely, are they using the same version of LabVIEW and Xilinx compile tools?

What is the target hardware? At what point in the compilation process does the compilation fail and what is the compilation status when it fails? What error (if any) do you see in the LabVIEW Compilation Status window when the compilation fails? This error is usually more descriptive.

Regards,

j_bou

[christian_w]

Try to delete the content of the D:\NIFPGA\JOBS folder and the compilation and corecache content  too and restart the build.

...worked for me

[Matthew_Kelton]

j_bou,

Right now, the lab PC has 2014, and the laptop has 2014 SP1, but I only installed SP1 before posting here as my last ditch effort to fix the issue.  Before that, they were both running the same version of LabVIEW and Xilinx tools.

The target is a cRIO-9068 with the following modules:

1 - NI 9476

2 - NI 9476

3 - NI 9476

4 - NI 9205

5 - NI 9403

6 - NI 9403

7 - NI 9205

8 - Empty

Right now, I am only utilizing the 9403 in slot 6, but all are defined int he FPGA.  Running FPGA Interface only, and the compilation is no where close to using up the full resources of the FPGA.

The compile lasts less than a minute.  I see the compiler make the job directory.  Here is the summary:

LabVIEW FPGA: The compilation failed due to a Xilinx error.

Details:
ERROR: [Ipptcl 7-5] XIT evaluation error: Invalid file name: d:/NIFPGA/jobs/J58nk9W_FdmlHyX/or9vuifc/dummy-project.srcs/sources_1/ip/ReallyLongUniqueName_ReallyLongUniqueName/ReallyLongUniqueName_ReallyLongUniqueName_ooc.xdc
ERROR: [Common 17-39] 'xit::add_ipfile' failed due to earlier errors.
CRITICAL WARNING: [IP_Flow 19-1747] Failed to deliver file 'c:/NIFPGA/programs/Vivado2013_4/data/ip/xilinx/blk_mem_gen_v8_1/ttcl/bmg_ooc_xdc.ttcl': ERROR: [Common 17-39] 'xit::add_ipfile' failed due to earlier errors.

ERROR: [Ipptcl 7-5] XIT evaluation error: Invalid file name: d:/NIFPGA/jobs/J58nk9W_FdmlHyX/or9vuifc/dummy-project.srcs/sources_1/ip/ReallyLongUniqueName_ReallyLongUniqueName/ReallyLongUniqueName_ReallyLongUniqueName.mif
ERROR: [Common 17-39] 'xit::add_ipfile' failed due to earlier errors.
CRITICAL WARNING: [IP_Flow 19-1747] Failed to deliver file 'c:/NIFPGA/programs/Vivado2013_4/data/ip/xilinx/blk_mem_gen_v8_1/hdl/mem_init_file.xit': ERROR: [Common 17-39] 'xit::add_ipfile' failed due to earlier errors.

ERROR: [IP_Flow 19-167] Failed to deliver one or more file(s).
ERROR: [IP_Flow 19-98] Generation of the IP CORE failed.

while executing
"generate_target synthesis $ip"
(file "C:\NIFPGA\jobs\J58nk9W_FdmlHyX\or9vuifc\coregen.tcl" line 50)
INFO: [Common 17-206] Exiting Vivado at Mon Apr 13 09:49:58 2015...
# exit
INFO: [Common 17-206] Exiting Vivado at Mon Apr 13 09:50:00 2015...

Compilation Time
---------------------------
Date submitted: 4/13/2015 9:48 AM
Date results were retrieved: 4/13/2015 9:50 AM
Time waiting in queue: 00:24
Time compiling: 00:50
- Generate Xilinx IP: 00:45

[Matthew_Kelton]

Christian,

Thanks for the suggestion, but it didn't make a difference.

Matthew

[christian_w]

I also have trouble to compile smallest FPGA VI's with LabVIEW 2014 SP1...here is what I did

- deinstall Xilinx Vivado compiler (LabVIEW 2014 SP1)

- install Xilinx compiler from DS2/2014 (LabVIEW 2014 f1)

This will work definitly

[christian_w]

This bug should be patched with the latest C-Module critical driver update for LabVIEW FPGA 2014 SP1. It was not a Xilinx bug but a problem with the intermediate files.

.. all my problems are gone 🙂

[Matthew_Kelton · Accepted solution]

So, I have finally determined what the problem has been.

I had created a Windows junction for several directories to port some files off to a second drive.  As far as Windows is concerned, C:\NIFPGA is exactly there, and is supposed to hide the fact that it's really D:\NIFPGA.

Well, apparently, it does not hide that well enough from some programs.  I noticed in the Xilinx log file it kept swapping between C:\NIFPGA and D:\NIFPGA.  So, I tried a Windows Symbolic Diretcory Link, which is similar to the Junction (from my research the junction is supposed to be the "better" one), and now it seems to work fine.

So, here's the lesson:  If you want to move that NIFPGA directory, either reinstall the system, or use a symbolic link to remap the directory, not a junction.