FPGA Checksum

[solarsd]

T-REX$:

Thanks for the reply. Could you explain in more detail how the current "start up app that is stored on the RT controller"? Does that mean it resides in some sort of flash memory on the FPGA controller card itself and gets loaded into the FPGA when power is applied?

[nathand]

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@solarsd wrote:

T-REX$:@T-REX$

Thanks for the reply. Could you explain in more detail how the current "start up app that is stored on the RT controller"? Does that mean it resides in some sort of flash memory on the FPGA controller card itself and gets loaded into the FPGA when power is applied?

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Those comments apply to real-time targets such as the cRIO that are full controllers and do have on-board flash drives. According to the help, some FPGA devices do include flash memory that can store a bitfile, but I'm not clear if that includes any PCI/PXI cards and I've never tried to use that feature with one of those cards.

[T-REX$]

Hey nathand and solarsd,

Actually, even the R-Series devices have onboard flash that let you have a bitfile load at boot. Check out the How Can I Have My FPGA VI Run At Boot? KB to see how to use the RIO device setup utility to download a bitfile to the onboard flash for any target (AFAIK).

One of the main differences between FPGAs and CPLDs is the volatility of FPGA fabric. Due to this, pretty much all FPGAs are paired with dedicated flash to hold bitfiles to load on power-up.

You can use the System Configuration API to download bitfiles to flash programmatically.