FPGA CLIPs: same ports, different realization

[Crowbar]

Hello, just want to clarify one moment regarding CLIP change on the fly without port replacement.

Suppose I have CLIP1 and CLIP2. They have different vhdl and constraint files but same ports, I'm also adding them to project with the same names.

Preparation steps:

1) Create a project

2) Import a CLIP1 to it (Target->Properties->Component-Level IP)

3) Add a clip to project tree (Target->New Component-Level IP->select imported CLIP1 instance)

4) Use this CLIP1 instance ports in a project vi's

Change steps:

1) Remove CLIP1 using import form (Target->Properties->Component-Level IP)

2) Import another CLIP2 (Target->Properties->Component-Level IP)

3) Do not touch ports in a project vi's

Is it correct as described above: to change CLIP using only import form without manual ports replacement on a BD?

Is it correct to move vi's with CLIP ports inside between different targets without ports replacement each time I place such a vi on a different target?

[TheXiadow]

Hello,

Whether or not there would be any issues would really depend on the hardware. If you import a CLIP into the project, it should automatically populate with the ports. With moving the VI around, different hardware could have different clocks and different settings, and thus it would depend on the hardware that you are working with.

Also, I did want to let you know that we do have some more specialized forums where you might be able to reach a more FPGA/CLIP knowledgeable audience! Just a tip if you're looking to get more responses 🙂