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FPGA Butterworth filter - why the conversions to fixed-point?

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I was looking through the FPGA Butterworth Filter Express VIs, and came across this code (after converting the Express VI to a subVI, and then opening the front panel):

FPGA Butterworth Filter.png

What's going on with the conversion to fixed-point for values that look like they should be integers (in the red boxes)? Why would these conversions be useful?

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Accepted by topic author nathand

These are micro-optimizations intended to help the synthesis tools minimize the number of bits used in these code paths. The iteration terminal is 32-bits wide, and also implies some logic to deal with what happens when the maximum value is reached. We saw some benefit from reducing this path to the minimum required width at the time this is written; I think this is likely still the case since the compiler doesn't generally know how many times a given loop is going to execute with a dynamic stop condition like this.

 

The counter width optimization is similar, taking advantage of the fact that we know we've restricted the memory space to use power-of-2 size circular buffers. Using the exact number of address bits lets us implement a roll-over counter with no extra logic; otherwise we would need to check the value and add a mux (Select) to reset the counter when it reaches the maximum value.

 

Normally the synthesis tools do a pretty good job of optimizing out unused bits, but these are two cases where we can help them out by being more explicit about what we actually need.

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