FIFO time out

[tlin067]

when I use a target-scoped FIFO I continually get my write fifo to time out. Does this mean that the FIFO is full and data will stop being written to memory or just some of the data at the end is lost as more is written in? How can i get around this?

I'm confused as to wheter my code is doing what i want it to do. I want to stream data from two analogue input channels and write to a target scoped FIFO. Then I want to read this data point by point when it is available and perform operations on it (second while loop). When i run code however, the fifo times out almost immediately. Is this bad?

Sorry for the silly questions I've been worrying about the actual operations required instead of getting to grips with the basics.  I have added my code if it helps.

Thanks very much,

Tom

[AdnanZ]

Hi Tom,

Timeout inputs the number of clock ticks the function waits for available space in the FIFO if the FIFO is full. A value of –1 prevents the function from timing out. A value of 0 indicates no wait.

Timed Out? returns TRUE if space in the FIFO is not available before the function completes execution. If Timed Out? is TRUE, the function does not add Element to the FIFO.

So, you lose the data because your queue is full which is understandable since you are spending relatively more time doing analysis than acquisition. If you need to get around it, then you need to increase the size of your FIFO or use more queues so you can reduce the time you spend to analyze the data.

[kotha_mahesh]

Hi sir,

   While am doing fpga and host configuration,if I place while loop in fpga block with in which fifo(host to target) read and fifo(target to host)  write functions are there.Here am getting the problem is when i replace while loop with SCTL(single cycle timed loop),I am getting error -50400....which is about time out.

   I have taken 100 elements to read and write to and from fpga target .can you resolve the problem or give me full understanding of number of elements versus time out errors...

  Here I am attaching files related to this problem.Please have a look at this.

[Bob_Schor]

I'm not sure where I learned this (probably in some LabVIEW Help text), but I recall that RT FIFOs are for getting the data out of the Real-Time loop, and if additional processing is needed, the FIFO read loop immediately puts the data into a conventional Queue as the Producer of a Producer/Consumer pair.  This way, the RT Loop gets "rid" of the data, there are no RT FIFO timeouts (because the FIFO is emptied as fast as it fills up, transferring the data to a conventional Queue (which provides the necessary buffering).

Bob Schor