FIFO Causes Analog Input Data To Switch

[jbart253]

I have a program that reads from two analog input pins on my sbRIO-9636 and logs the voltage data as well as time data to an excel file when a button is pressed. I want the FPGA portion of this program to run continually. The problem I am running into is that, when it runs continually and I try to access it, the data is switched. The first time I run the program on the host computer and the FPGA program hasn't run yet, it works just fine. When I run the program on the host computer and the FPGA program has been running, then the data is switched. I have attached pictures of my charts to show this. In these pictures, I am applying a sine wave to AI0 and AI1 is attached to ground. The first picture shows when the FPGA program hasn't been running and all VIs start at the same time. The second pictures shows when the FPGA program has been running and then I try to run the host VI. Also a note, I am trying to read at about 200k data points a second (100k data points per channel per second since it's aggregated sampling). I believe it is something with the FIFO, maybe overflow or something, but I really have no idea how to fix it. Any help would be greatly appreciate. I have also attached the Host VI and FPGA VI as well as the necessary subVIs for the host.

[jbart253]

Append Array.vi is a circular buffer that keeps updating my array holding all of my data points since I only want a certain amount before the button is pressed. Update Array.vi appends data to the array after the button has been pressed. After all of this it is written to the excel file (though this part is unecessary for the problem at hand).

[jbart253]

Also, the Analog Input Data FIFO has a requested number of elements value of 1023 with a fixed point data type. 

[Reyquaza]

Hi jbart,

After looking over it a few times, your code looks fine. Do the charts switch every time you start the host second, or does it sometimes stay the same? I ask because there may be chance that you're starting to read the DMA FIFO in a different place depending on when you start the host VI. If it only happens sometimes, then we just need to find a way to ensure that you always start reading with the same sample.

[jbart253]

It never switches back. Once it switches from what you see in the charts in the first picture to what you see in the charts in the second picture, it will never change back to what you see in the first picture no matter how many times you run the code. There is no switching back and forth. It's a permanent thing until you reset the FPGA. So I only see the correct output on my charts on the first run of the host (as long as the FPGA hasn't been running) and then I see the incorrect, reversed output from there after until I reset the FPGA. 

[jbart253]

Update: I looked at the element remaining portion of my analog data FIFO and on the first run is says 16 elements remaining. When it runs afterwards (as long as the FPGA has been running) it then says 31 elements remaining. This must be my issue?

[Reyquaza]

This makes sense. You're always reading an even number from the FIFO, so if there's an odd number of elements remaining, that means your Read is off by one element, causing the graphs to switch because the array is off by one element. Here's what I think is happening.

1. You run both together, everything is fine.

2. You stop the Host VI, which stops reading, so your buffer fills up.

3. Your buffer is an odd number (the default size is 1023) so rather than writing, for example, 01010101, you write 0101010.

4. When you start reading again, you read an even number, but since you have an odd number of elements in your FIFO, the graphs are switched.

Can you configure the settings of the DMA FIFO in your project and try an even number of elements?

[jbart253]

That makes sense! Because I am doing a Target to Host - DMA FIFO, it automatically implements it via block memory. So when I choose a value for requested number of elements, it coerces to a valid value and shows the actual number of elements which is always odd. Is there any way around this?