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Error while creating CLIP component via VHDL file

Hi users,

currently I'm training with LabVIEW FPGA using Version 2016 and a sbRIO-9651 development kit. When I tried to include a CLIP component with a VHDL code from this NI tutorial I have got the following error during "CheckSyntax" on page 3 of 8 in the setup window:

 

"Extracting top-level synthesis file information. Please wait...

Processing files...
Assembler messages:
Error: can't open xsim.dir/DemoClipAdder/obj/xsim_1.win32.as for reading: No such file or directory
Assembler messages:
Error: can't open xsim.dir/DemoClipAdder/obj/xsim_0.win32.as for reading: No such file or directory
Fix the above error and check syntax again."

 

I set up the CLIP according to this NI tutorial and set simulation behavior to "Exclude from simulation model".

Searching the NI forums and the web for the above stated error was not successful.

 

Does anyone encountered this problem and know how to solve it?

 

 

 

 

 

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I have run into this exact set of error messages walking through the tutorial and testing my own IP.  Has anyone found a solution for this?

 

 

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