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Elapse time express vi

So i just wanted to post my final disign for my timer...

Even though this disign does not use the "Elapse Time Express VI" LabVIEW provides, it might help someone get a better understanding of how to go about building THEIR design...

I mean after all i most likely would not have come up with this diesign if i havnt stubbled onto this thread 😃

 

The trick is asking the right questions to get the answer your looking for...

 

Anyways, remember im a noob to LabVIEW, but i already had my idea of what i wanted to make and how it was supposed to function i just didnt know how to disign it to work and function properly...

 

So when i opened up LabView and was searching for some kind of timer i found this Elapse Time (im going to call it a plug-in for lack of a better word). I was all excitedbecause i figured i can just use that and wire it up they way i wanted... but i still didnt really understand what the heck was going on in the circuit. Once Stevem181 provided an alternate whay to build a "home made" circuit it opened alot of doors and got me to somewhat understand LabVIEW better. unfortuneantly i was building this design to run on an cRIO9636 using the FPGA. As you would know the FPGA did not like the design and came up with all kinds of errors saying it didnt support any of the fuctions *sigh*.

 

So the main lesson i learned here is build your design based on the platform your going to put it on! LOL

 

So if you comming here looking to answer a question, any of the above examples are great... but if i could share anything that i learned from thsi project its understand what fuction are supported for the system you are building it for =P

 

Anyways thanks for all the help, im ready for the next part of this design (unless someone has any suggestions) i still dont fully understand how to prevent loops from consumming too much load from the cpu or is this design is efficiant... BUT ITS WORKING =P

 

 

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Message 31 of 42
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Hi AEP3,

 


So the main lesson i learned here is build your design based on the platform your going to put it on! LOL


Well, the main lesson learned should be "go through all basics tutorials provided for each target by NI" instead - before starting to program…

 


but if i could share anything that i learned from thsi project its understand what fuction are supported for the system you are building it for


LabVIEW adapts the functions palettes to the target of the current VI. You immediatly see which functions are supported for a certain target…

 


i still dont fully understand how to prevent loops from consumming too much load from the cpu or is this design is efficiant... BUT ITS WORKING


On the FPGA target there is no "cpu consuming too much load" problem! The only problem you have is: does the FPGA provide enough slices/fabric for your VI and does it  fulfill all timing constraints…

 

On your VI:

Why do you mix datatypes (I16 and U16)? Why don't you stick with U16 with all terminals and constants?

Best regards,
GerdW


using LV2016/2019/2021 on Win10/11+cRIO, TestStand2016/2019
Message 32 of 42
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Hello Gerd,

 

Well i thought the "basic tutorials" where the first 4 or 5 tutorials they first have me follow after the install...

The only thing i learn with those were that i could follow direction... they werent teaching my really why i wrapped the program in a while loop and other things... please if you going to tell me to visit the basic tutorials before i try and program send me to a link, you just leaving me hanging there... =/

 

Also i do now realize that there are different pallets for different targets and when you create it in there it automatically adjust accordingly... but i didnt know that at the time -_-

 

please elaborate on this:

"On the FPGA target there is no "cpu consuming too much load" problem! The only problem you have is: does the FPGA provide enough slices/fabric for your VI and does it  fulfill all timing constraints…"

 

As for the data types (I16 and U16) i did realize they were different... ill have to look into why one is better then the other or the differences

 

Thanks!

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Message 33 of 42
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So i spent a little time this morning and found what i hope you (Gerd) are referring to as the "basic tutorials" here:

LabVIEW Basics

 

I came across the section thats talks about numeric data here:

Numeric Data

From what i understand i should be using unsigned integers since im not dealing with negative numbers, right?

I went ahead and made the following changes:

- All numeric constants to (U8) sicne the number im using is "0" i dont think it needs to be bigger then 8bits

- "Set Time" and "Run Time" to (U16), since im only dealing with 4 decimal places i dont need to go any higher then that right?

 

But the question still remains:

"does the FPGA provide enough slices/fabric for your VI and does it  fulfill all timing constraints…"

 

Im going to see what i can find, but if you could elaborate on this for me that would be great 😃

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Message 34 of 42
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Hi AEP3,

 

The LabVIEW Basics resource listed above is quite a nice compilation of information for an introduction into programming using LabVIEW. I also wanted to make sure that you have access to this document Getting Started with LabVIEW FPGA. I think this may help with your application which entails using LabVIEW FPGA specifically.

 

When GerdW refers to the questions “does the FPGA provide enough slices/fabric for your VI and does it fulfill all timing constraints…” he is referring to the compilation process for FPGA development.

 

Remember, when we are programming an FPGA VI, ultimately the functionality will be implemented using hardware. Since the FPGA has a limited number of hardware resources the compiler will let us know if the FPGA has enough resources to implement the functionality we defined in the VI. The FPGA also has strict timing requirements based on our program and the compiler will also make sure that all timing constraints are met. I think this resource from the LabVIEW 2012 FPGA Module Help may aid in my broad overview: Understanding the LabVIEW FPGA Compile System (FPGA Module)

Sam Burhans
Senior Product Manager
National Instruments
Message 35 of 42
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HI CoffeeBreak! (love the name btw)

 

Thank you for taking some time to help clear up some of the questions at hand 😃

 

As for your link "Getting Started with LabVIEW FPGA" i actually came across that tutorial when trying to get the original code i wrote that ran fine on my PC, but when i tried to load it to the FPGA all the errors came up, so i did some research came across that tutorial, followed the steps, and made the following changes to my code in order for it to run on the FPGA...

 

at this stage of my first experience with programming in LabVIEW for an FPGA VI on the sbRIO i think i have a very basic understanding about how to go about creating my program... but i still have doubts that my program will run efficiently or how to optimize it further... i know this probably will take time but i just don’t want to be picking up bad habits if you know what i mean.

 

I quickly glanced at the second link you posted "Understanding the LabVIEW FPGA Compile System (FPGA Module)", ill give it a more thorough look tomorrow, but i remember reading somewhere in a tutorial (sorry im not able to link what i am about to refer to) about if you are using 2 separate loops in the same VI, 1 loop can potentially bottle neck the other? i am not sure how accurate that reference is, i just cannot seem to find the tutorial that talk about that... you have to excuse me im currently juggling a few different projects so i apologize for being all over the place...

 

i know this might start becoming off topic now that i got the timer program to work, now its about is my program efficient and if not how should i go about to optimize it, then once i know its efficient i need to start implementing the other functions and processes it will be controlling... so i might need to find another thread or start one of my own for those questions -__-

 

but im attaching the latest version running as intended, and i actually have it controlling the machine it is going to be integrated into… this program completely replaces the original timer I had in my machine 😃

 

I do want to thank everyone that did reply 😃 this program is far from done so more questions are to come =P

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Message 36 of 42
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Hi AEP3,

 

I am not sure what material you referenced for the information in regards to parallel loops, but maybe I can help shed some light on the subject.

 

There is a bit of a difference between programming using LabVIEW and deploying LabVIEW FPGA VIs, but I’ll try and cover some of the basics. In LabVIEW parallel while loops, for example, are automatically run in parallel based on the CPU in your machine. Therefore, they will be running asynchronously in a  top level VI. In LabVIEW FPGA code, remember, all parallel code is mapped to different hardware resources on the FPGA. Therefore these loops will also run independently.

 

However, if you have two independent processes within the same while loop the loop execution rate will be bottlenecked by the slowest process.

 

Does that answer your questions about parallel loops in LabVIEW and LabVIEW FPGA?

Sam Burhans
Senior Product Manager
National Instruments
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Message 37 of 42
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Hello again CoffeeBreak,

I was able to find what i read about loop execution...

It was in this tutorial page 45 step 14: NI LabVIEW RIO Evaluation Kit

It reads:

 

14. Without setting timing in the while loop it will execute as fast as it can, potentially starving resources allocated to the other loop. To avoid this insert a Wait Until Next ms Multiple (Functions»Programming»Timing) function inside the loop. Right-click on its millisecond multiple input and select Create»Constant.

Enter a value of 100 in the constant to execute the loop every 100 milliseconds.

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Message 38 of 42
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Hi AEP3,

 

Sorry for the late response, somehow I wasn’t notified of your response on the forum.

 

Ah, well thank you for pointing out the exact reference material you used for this knowledge. You are correct that in the Real-Time programming if we do not place a timer in the loop we will starve other processes of CPU resources. This is due to the fact that if we do not place a timer in the loop we are essentially telling the Real-Time Operating System to run this loop as fast as possible. Obviously the implications of that action leave other processes with less processing time.

Sam Burhans
Senior Product Manager
National Instruments
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Message 39 of 42
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Its cool, i havnt been ver active on here lately myself...

Been researching my next phase in this design, i started a new thread here: FPGA Fundamentals (sbRIO9636)

 

Now that i got my timmer to tick... added controls for the safty check circuit, and have it all run for a set period on time based on the operator's input i want to be able to save the run time to a file (on the sbRIO preferably for a hard copy backup) and upload to a server. Essentially it will just be the "U16" Run Time data line that i want to save to a file so i dont think it is going to be big files to save and/or transfer. I bring up timming contraints and loop proccesses because from what i have read so far i tlooks like im going to have to creat a Real-Time VI that will collect the data from the FPGA in order to save/send data to where i need it to go... i had like 20 different tabs open yesterday with different references on how to go about making this happen... it feels like i have done a full 360 and now back to square one... lol just when i thought i had a grasp on this =(

 

So let me take a swing at it:

 

FPGA VI - this VI run on the FPGA on the sbRIO itself

RT VI - this VI can be embeded on the sbRIO but it runs on your Computer?

 

... or am i completely wrong

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