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ERROR:MapLib:979 - LUT4 symbol

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Do you have an update on thisone?

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Message 11 of 23
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Still nothing?

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Message 12 of 23
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Hello,

 

Sorry for the late reply, but I did not receive a notification of the last three posts.

I only received the e-mail you sent us today.

 

I did some further research.

The error could be caused by a bug in the Xilinx Compiler:

http://www.xilinx.com/support/answers/33744.htm

 

Bu trying to change the Xilinx Options I saw that it seems to be not directly possible (for this target) from the LabVIEW Project like specified at http://digital.ni.com/public.nsf/allkb/EE940C191DDCE9CE86256E5500783A4D

 

Also I do not seem to be able to find the .opt file.

 

I'm going to look further and inform you of what I find.

 

Kind Regards,

Kind Regards,
Thierry C - CLA, CTA - Senior R&D Engineer (Former Support Engineer) - National Instruments
If someone helped you, let them know. Mark as solved and/or give a kudo. 😉
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Message 13 of 23
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Hello,

 

Sorry for the late reply, but I did not receive a notification of the last three posts.

I only received the e-mail you sent us today.

 

I did some further research.

The error could be caused by a bug in the Xilinx Compiler:

http://www.xilinx.com/support/answers/33744.htm

 

By trying to change the Xilinx Options I saw that it seems to be not directly possible (for this target) from the LabVIEW Project like specified at http://digital.ni.com/public.nsf/allkb/EE940C191DDCE9CE86256E5500783A4D

 

Also I do not seem to be able to find the .opt file.

 

I'm going to look further and inform you of what I find.

Kind Regards,
Thierry C - CLA, CTA - Senior R&D Engineer (Former Support Engineer) - National Instruments
If someone helped you, let them know. Mark as solved and/or give a kudo. 😉
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Message 14 of 23
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Hello Vincent,

 

I've been out of office last week so my apologies for the delay.

 

I have some questions/requests for you:

- Can you try removing both boolean arrays (control and indicator) from the front panel of the FPGA VI? Does this make the compilation work?

- Can you try replacing the array by seperate controls and then do the compilation?

- If one of these work, can you test the functionality to see if it still performs correctly?

 

The problem itself seem to be situated in the CLIP itself, where the signals connected to the array get trimmed.

Currently some of my R&D colleagues in the US are also working in parallel on this issue.

Kind Regards,
Thierry C - CLA, CTA - Senior R&D Engineer (Former Support Engineer) - National Instruments
If someone helped you, let them know. Mark as solved and/or give a kudo. 😉
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Message 15 of 23
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Hi Thierry

 

Thanks for your feedback!

 

- The first question: It compiles correct when I remove the boolean control and indicator, I will test it tomorrow on my development board ... at this time no luck with SP3E driver on Windows 7 (64bit)

 

 

Kind regards

Vincent Claes

http://pwo.fpga.be

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Message 16 of 23
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Solution
Accepted by topic author Vincent_Claes

Hello Vincent,

 

After some further research together with my R&D-colleagues in the US the underlying reason has been found.

 

The problem is with the XML file and the fact that two of the three vhd files were written with an upper case ".VHD" extension rather than lower case. The bug/problem is that LabVIEW FPGA does not recognize the upper case and does not send these files to the compile worker.

 

All you have to do in this case is edit the XML file and replace the upper case "VHD" with lower case "vhd" for the two file extensions. After this you have to go back to the XML declaration in the FPGA target and select "rescan for files". After you do this the compilation is successful.

 

This will actually solve your problem. The previous solution would only trim/remove all unused code.

Kind Regards,
Thierry C - CLA, CTA - Senior R&D Engineer (Former Support Engineer) - National Instruments
If someone helped you, let them know. Mark as solved and/or give a kudo. 😉
Message 17 of 23
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Hi Thierry

 

 

Thanks for your great work, this solution works perfect, is there any chance on having the Spartan3E driver running on Windows 7 (64bit)? Or is it possible to port the driver to a new Xilinx XUP board (Digilent Atlys with Spartan6?) since the SP3E boards are rather old and become sold out soon.

 

 

Thanks

 

Kind regards

Vincent Claes

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Message 18 of 23
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Hello Vincent,

 

I've contacted my American colleagues and for the moment there's no 64 bit driver for the Spartan3E planned.

Drivers for newer XUP boards are also not yet planned.

 

One thing you can do is propose the creation of these new drivers on LabVIEW FPGA Idea Exchange.

You can also do these kind of suggestions for other NI software on the other parts of the NI Idea Exchange .

Kind Regards,
Thierry C - CLA, CTA - Senior R&D Engineer (Former Support Engineer) - National Instruments
If someone helped you, let them know. Mark as solved and/or give a kudo. 😉
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Message 19 of 23
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Hello ThiCop,

 

Could you please tell me where I can find xml file and what is the name of xml file that I need to edit to solve this problem.

 

King Regards,

 

Damir Hamidovic

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Message 20 of 23
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