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ERROR:MapLib:979 - LUT4 symbol
Solved!
Vincent_Claes
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10-27-2010 02:00 PM
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When I try to compile my LV FPGA code (using LV 2010) I get the following errors: (In LV 8.6 It worked great....)
Code: LV FPGA code problem
ERROR:MapLib:979 - LUT4 symbol "LvFpgaWindow/theVI/leds_array_ind_0/PlainIndicator.PlainIndicator/cQ_mux0000 <0>1" (output signal=LvFpgaWindow/theVI/leds_array_ind_0/PlainIndicator.PlainIndicator/cQ_m ux0000<0>) has input signal "LvFpgaWindow/theVI/n_While_Loop_7892_Diagram/n_NiFpgaAG_00000008_SequenceFra me_Diagram/n_nirviEIOImplementation_xnode_91_Diagram/cSyncRegister<7>" which will be trimmed. See Section 5 of the Map Report File for details about why the input signal will become undriven. ERROR:MapLib:979 - LUT4 symbol "LvFpgaWindow/theVI/leds_array_ind_0/PlainIndicator.PlainIndicator/cQ_mux0000 <1>1" (output signal=LvFpgaWindow/theVI/leds_array_ind_0/PlainIndicator.PlainIndicator/cQ_m ux0000<1>) has input signal "LvFpgaWindow/theVI/n_While_Loop_7892_Diagram/n_NiFpgaAG_00000008_SequenceFra me_Diagram/n_nirviEIOImplementation_xnode_91_Diagram/cSyncRegister<6>" which will be trimmed. See Section 5 of the Map Report File for details about why the input signal will become undriven. ERROR:MapLib:979 - LUT4 symbol "LvFpgaWindow/theVI/leds_array_ind_0/PlainIndicator.PlainIndicator/cQ_mux0000 <2>1" (output signal=LvFpgaWindow/theVI/leds_array_ind_0/PlainIndicator.PlainIndicator/cQ_m ux0000<2>) has input signal "LvFpgaWindow/theVI/n_While_Loop_7892_Diagram/n_NiFpgaAG_00000008_SequenceFra me_Diagram/n_nirviEIOImplementation_xnode_91_Diagram/cSyncRegister<5>" which will be trimmed. See Section 5 of the Map Report File for details about why the input signal will become undriven. ERROR:MapLib:979 - LUT4 symbol "LvFpgaWindow/theVI/leds_array_ind_0/PlainIndicator.PlainIndicator/cQ_mux0000 <3>1" (output signal=LvFpgaWindow/theVI/leds_array_ind_0/PlainIndicator.PlainIndicator/cQ_m ux0000<3>) has input signal "LvFpgaWindow/theVI/n_While_Loop_7892_Diagram/n_NiFpgaAG_00000008_SequenceFra me_Diagram/n_nirviEIOImplementation_xnode_91_Diagram/cSyncRegister<4>" which will be trimmed. See Section 5 of the Map Report File for details about why the input signal will become undriven. ERROR:MapLib:979 - LUT4 symbol "LvFpgaWindow/theVI/leds_array_ind_0/PlainIndicator.PlainIndicator/cQ_mux0000 <4>1" (output signal=LvFpgaWindow/theVI/leds_array_ind_0/PlainIndicator.PlainIndicator/cQ_m ux0000<4>) has input signal "LvFpgaWindow/theVI/n_While_Loop_7892_Diagram/n_NiFpgaAG_00000008_SequenceFra me_Diagram/n_nirviEIOImplementation_xnode_91_Diagram/cSyncRegister<3>" which will be trimmed. See Section 5 of the Map Report File for details about why the input signal will become undriven. ERROR:MapLib:979 - LUT4 symbol "LvFpgaWindow/theVI/leds_array_ind_0/PlainIndicator.PlainIndicator/cQ_mux0000 <5>1" (output signal=LvFpgaWindow/theVI/leds_array_ind_0/PlainIndicator.PlainIndicator/cQ_m ux0000<5>) has input signal "LvFpgaWindow/theVI/n_While_Loop_7892_Diagram/n_NiFpgaAG_00000008_SequenceFra me_Diagram/n_nirviEIOImplementation_xnode_91_Diagram/cSyncRegister<2>" which will be trimmed. See Section 5 of the Map Report File for details about why the input signal will become undriven. ERROR:MapLib:979 - LUT4 symbol "LvFpgaWindow/theVI/leds_array_ind_0/PlainIndicator.PlainIndicator/cQ_mux0000 <6>1" (output signal=LvFpgaWindow/theVI/leds_array_ind_0/PlainIndicator.PlainIndicator/cQ_m ux0000<6>) has input signal "LvFpgaWindow/theVI/n_While_Loop_7892_Diagram/n_NiFpgaAG_00000008_SequenceFra me_Diagram/n_nirviEIOImplementation_xnode_91_Diagram/cSyncRegister<1>" which will be trimmed. See Section 5 of the Map Report File for details about why the input signal will become undriven. ERROR:MapLib:979 - LUT4 symbol "LvFpgaWindow/theVI/leds_array_ind_0/PlainIndicator.PlainIndicator/cQ_mux0000 <7>1" (output signal=LvFpgaWindow/theVI/leds_array_ind_0/PlainIndicator.PlainIndicator/cQ_m ux0000<7>) has input signal "LvFpgaWindow/theVI/n_While_Loop_7892_Diagram/n_NiFpgaAG_00000008_SequenceFra me_Diagram/n_nirviEIOImplementation_xnode_91_Diagram/cSyncRegister<0>" which will be trimmed. See Section 5 of the Map Report File for details about why the input signal will become undriven.
Any advice???
Thanks very much!
Vincent
Solved! Go to Solution.
11-01-2010 03:54 AM
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anyone?
12-01-2010 12:27 PM
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When using Xilinx Tools the synthesization works fine... Anyone?
Nico_support
NI Employee (retired)
12-02-2010 04:54 AM
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Hello Vincent Claes,
I've looked in our database and found a similar problem.
Can you please take a look at the following link: http://digital.ni.com/public.nsf/allkb/BB56082D6A521196862574DC006BE858?OpenDocument
Can you tell if your target is supported?
Kind regards,
Nico Lammens
NIBE Applications Engineering
12-13-2010 02:04 PM
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Hi Nico
The strange thing is I have implemented this design using the VHDL code and Xilinx ISE tools and this integration is working. When using the LabVIEW FPGA module/CLIP node it is not working... Maybe some features of the CLIP node are not supported for this Xilinx Spartan3E Starter board ???
ThiCop
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12-28-2010 08:19 AM
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Hello Vincent,
You mention that you ahve implemented this already with the Xilinx ISE Tools.
By this you mean without using LabVIEW FPGA?
Which version of the Xilinx ISE Tools did you use to implement this without LabVIEW?
Kind Regards,
Thierry C - CLA, CTA - Senior R&D Engineer (Former Support Engineer) - National Instruments
If someone helped you, let them know. Mark as solved and/or give a kudo. 😉
Thierry C - CLA, CTA - Senior R&D Engineer (Former Support Engineer) - National Instruments
If someone helped you, let them know. Mark as solved and/or give a kudo. 😉
ThiCop
Trusted Enthusiast
12-28-2010 08:19 AM - edited 12-28-2010 08:20 AM
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Hello Vincent,
You mentioned that you have implemented this already succesfully with the Xilinx ISE Tools.
By this you mean without using LabVIEW FPGA?
Which version of the Xilinx ISE Tools did you use to implement this without LabVIEW?
Kind Regards,
Thierry C - CLA, CTA - Senior R&D Engineer (Former Support Engineer) - National Instruments
If someone helped you, let them know. Mark as solved and/or give a kudo. 😉
Thierry C - CLA, CTA - Senior R&D Engineer (Former Support Engineer) - National Instruments
If someone helped you, let them know. Mark as solved and/or give a kudo. 😉
12-29-2010 09:26 AM - edited 12-29-2010 09:27 AM
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ISE 12.3, but it is possible with all versions of ISE I think...
ThiCop
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12-29-2010 09:43 AM
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The default compilers used for the Compilation of a LabVIEW FPGA 2010 VI are the Xilinx ISE 11.5 and Xilinx ISE 10.1 (depending on which kind of target you are using).
It could be that the functions you're trying to implement are not supported by ISE's older than 12.x .
Which FPGA target are you using?
Kind Regards,
Thierry C - CLA, CTA - Senior R&D Engineer (Former Support Engineer) - National Instruments
If someone helped you, let them know. Mark as solved and/or give a kudo. 😉
Thierry C - CLA, CTA - Senior R&D Engineer (Former Support Engineer) - National Instruments
If someone helped you, let them know. Mark as solved and/or give a kudo. 😉
12-29-2010 09:47 AM - edited 12-29-2010 09:50 AM
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my target is a SPARTAN3E FPGA (from the Xilinx Starter board)
SPARTAN3E devices are supported from ISE version 7.1 and up
You can try to open http://pwo.fpga.be/LabVIEW/ (solution lab 4 that worked fine on LV 8.6)
If I try to reopen the solution in 2010 I doesn't work anymore so it's probably an issue on the NI LV backend of LV FPGA
