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Does not compile on LV 2013, but works fine on LV 2012 SP1

I have an FPGA VI that compiles without issue with LV 2012 SP1, but does not work with LV 2013 and Xilinx Tools version 14.4. Why is this happening? I have attached the compiler log file.

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ba_0101,

 

2012 SP1 and 2013 both use different versions of the xilinx compilation tools. As we don't produce that software it's hard to say exactly what may have changed in their implementation that is causing the compilation to fail. A quick look at the logs uncovers this error during the placement phase:

 

ERROR:Place:120 - There were not enough sites to place all selected components.
   Some of these failures can be circumvented by using an alternate algorithm
   (though it may take longer run time). If you would like to enable this
   algorithm please set the environment variable XIL_PAR_ENABLE_LEGALIZER to 1
   and try again 

It looks to me like this error stems from this:

 

ERROR:Place:543 - This design does not fit into the number of slices available
   in this device due to the complexity of the design and/or constraints.

Which is a simple resource overmapping error. It looks like your design is rather large based on the rest of the logs. Am I correct in assuming this? During the compilation, what do the pre-synthesis device utilization reports estimate?

 

With large designs it is common to sometimes have successful compilations and sometimes not due to the random nature of the compiler during the place and route phases. Does the design consistently fail in 2013 accross several compilation attempts?

 

If you continue to see consistent failures, Xilinx's support documentation for this error suggests using setting an environment variable within the compile tools to use a different algorithm in the P&R phase. According to the documentation, this algorithm may take longer to execute, however it should improve the likelihood that your design successfully compiles. 

 

Additionally, if the design is just over utilization, you may benefit most by searching your design for areas that could be quickly and easily optimized to decrease resource utilization. I hope this information helps, please post back if you have any further questions.

 

Nick C | Software Project Manager - LabVIEW Real-Time | National Instruments
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During compile it states the design uses over 100% of resources and may not fit, but in LV 2012 SP1 it always manages to successfully compile. In LV 2013 with Xilinx Tools 14.4 it consistently fails. How do I change environmental variables? Can I force LV 2013 to revert to an older version of Xilinx Tools?

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You cannot use an older version of the xilinx tools with LabVIEW 2013. The Xilinx support document I linked points to instructions here on how to change environement variables in the Windows OS.

 

You will need to look for this variable:    XIL_PAR_ENABLE_LEGALIZER

 

Change it's value to "1"

Nick C | Software Project Manager - LabVIEW Real-Time | National Instruments
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@ba_0101 wrote:

During compile it states the design uses over 100% of resources and may not fit, but in LV 2012 SP1 it always manages to successfully compile. In LV 2013 with Xilinx Tools 14.4 it consistently fails. How do I change environmental variables? Can I force LV 2013 to revert to an older version of Xilinx Tools?


The compiler will perform many passes of optimization to try to get code to fit.  In the past I have seen compilations that are 135% fit, but take a very long time to compile.  What makes this a little bit of an issue is when compiling it will finish and say it used up 99% of the resources, but that might mean we can still a bunch more code before compilation will fail.  The optimization is a little random from what I've seen.  I have seen it where I compile and it fails, then try again changing nothing and it will fit.  

 

You must be right on the edge, and some changes in the compiler maybe made it less rigurous with optimization.  I believe that in newer versions of LabVIEW (2010 or so and newer) you can specify under the build specifications how hard the compiler will try to make the code fit.  You may want to optimize your code, and change these settings.

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I have tried selecting different combinations of compile options under the FPGA build but nothing has worked thus far. Again, everything compiles without issue on LV2012. It must be due to a change with the latest Xilinx 14.4 tools. My design does state that it is over 100% when estimating, but with LV 2012 it would always keep crunching and make it fit. Total compile time on LV2012 was under 30 minutes.

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ba_0101,

 

Any chance you can post your code or pm me your code so I can take a look and see if there are any optimizations I would recommend?

 

Unfortunately we're at the mercy of the compiler when it comes to this type of thing. If you've set the compiler optimization to resource utilization and that has no effect, the only thing left for us to do is optimize until the design fits. 

 

Did you have a chance to try changing the environment variable as I recommended from Xilinx's documentation?

Nick C | Software Project Manager - LabVIEW Real-Time | National Instruments
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