02-23-2016 07:20 PM
I'm wondering about the status of the FPGA operation when the controller boots to "Safe Mode"?
It would be nice if the FPGA would run without the RT system. My 9081 runs the Pharlap system and I have crashes when cause the system to go to safe mode.
I have written my FPGA code to recover from a reboot into a mode that should be 'safe' with respect to my hardware and system.
Can somebody enlighten me on how the Crio handles this?
Thanks,
Jim
02-24-2016 07:05 AM
Hmm, how can you crasch the RT so it boots into safe mode?? Are you sure the Safe mode DIP switch is in the OFF position?
Regarding the FPGA:
It depends on how you load the FPGA code. If the RT target is responsible for starting the FPGA code, then the RT code needs to be running. However, it is possible to download the code to the FPGA flash, and make it run as soon as it is powered. See this guide:
How Can I Have My FPGA VI Run At Boot?
http://digital.ni.com/public.nsf/allkb/BC513C2A0DC29C89862574BF0002B0B9
03-02-2016 10:32 PM