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Does FPGA run when Crio boots to Saft Mode?

I'm wondering about the status of the FPGA operation when the controller boots to "Safe Mode"?

 

It would be nice if the FPGA would run without the RT system.  My 9081 runs the Pharlap system and I have crashes when cause the system to go to safe mode. 

 

I have written my FPGA code to recover from a reboot into a mode that should be 'safe' with respect to my hardware and system. 

 

Can somebody enlighten me on how the Crio handles this? 

 

Thanks,

 

Jim

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Hmm, how can you crasch the RT so it boots into safe mode?? Are you sure the Safe mode DIP switch is in the OFF position?

 

Regarding the FPGA:

It depends on how you load the FPGA code. If the RT target is responsible for starting the FPGA code, then the RT code needs to be running. However, it is possible to download the code to the FPGA flash, and make it run as soon as it is powered. See this guide:

 

How Can I Have My FPGA VI Run At Boot?

http://digital.ni.com/public.nsf/allkb/BC513C2A0DC29C89862574BF0002B0B9

 

Best Regards

Alex E. Munkhaus
Certified LabVIEW Developer (CLD)
System Engineer
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Thanks for the reply,
I'm pretty sure the dip switch is set properly, I've checked it in the past. A good thing to revisit though.

I think the crash occurs when I'm running low on hard drive space. I'm writing a lot of data and need to automate the transfer too, haven't been able to spend the time to get the ftp data transfer going.
Hopefully we will soon be sending the data to an Oracle database, another thing to figure out once our space and data stricture are determined.

I'll try this and get back, I couldn't find this post again until I received an email from the forum.

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