Do I need to define multiple FIFO's to sync a master loop to three other parallel loops?

[JOmega]

If I have one loop generating a waveform and I want, say three other parallel loops to fetch values from that first loop via a VI-defined FIFO, do I need to place three separate FIFO 'write' elements (essentially defining three different FIFOs) in the first loop that correspond to three FIFO 'Read' elements in each of the three loops that are accessing data from the first loop?

[crossrulz · Accepted solution]

The problem with using a single FIFO is that when a value is read, that value is gone.  The other loops won't see that element.  And since it sounds like you are talking FPGA as well, you would have to worry about Arbitration as well.

You need a different FIFO for each loop you are sending to.