Discrete Transfer Function Direct VI - Input/Output Numerical Limits?

[johnsoja]

I'm using the Discrete Transfer Function Direct VI on a NI FPGA board.  The filter is working perfectly as designed within a certain input range.  However, once I reach some input level, the output appears to be wrapping back in some manner.  In other words, the dc gain (output) tracks the input up to a certain level, but once it reaches a threshold value (shown below), the output reverses and starts to go lower despite the input going higher.

My setup is as follows : Filter is running (sampled) at 20kHz.  Filter config is 1st order with numerator coefficients (-28.3, 28.57) and denominator coefficients (-0.7304, 1).  These coefficients produce a lead/lag filter with zero at 35Hz and pole at 1000Hz. 

Behavior : As I input fixed point values into the filter, the static (dc) output tracks as expected up to a certain magnitude input.  However, when I get to an input of  approximately 1147 and higher, the output reverses direction and begins to get lower.  Below are some example inputs and outputs :

Input    Output

100      100.148

500      500.741

1000    1001.48

1140    1141.69

1146    1147.7

1147    1146.91

1148    1119.34

1175    374.991

1188    16.5997

My question is what is causing this gain reversal once I reach a particular input level?  What are the input/output limitations of this transfer function block?

Thanks,

Joel

[ikelli]

Hi Joel,

Would you be able to attach your code for this?  I cannot find any documentation about the input/output limitations of this function, but if I can look at the code it will make it easier to see why you might be seeing this behavior. 

[johnsoja]

Thanks Kelli for taking a look.  I've attached a zip file with the project file, fpga vi, and host vi. 

Joel

[johnsoja]

Kelli,

Apologies for the confusion, but I attached the wrong version code previously.  I have removed the old zip file.  The attached file (code_correct.zip) is the version you should evaluate.

Joel

[DECONN]

Hi Joel,

I took a look at your code and created a simplified version to see if I could replicate it, and it did (see attached).

I also took a closer look at the Discrete Transfer Function Direct.vi (see image below) and stepped through it by setting the FPGA to "Simulation Mode" in the project. This allows for probe, breakpoints and Highlight Execution using simulated I/O. It appears that the Fixed Point values within the function saturate to 32768 if a number overflows. An overflow does occur at the first multiplication (see section A of image) using an input >1146. For example, your model calls for a numerator of "28.57" so this multiplied by an input of "1147" gives an overflow of 32769.79. However, our negative values (section B) keep going lower. Therfore, this is the reason why you tend to see the output continually decrease.

That said, I'm not an expert in this functionality so I'm not sure if the Transfer Function Model needs to be adjusted, or the algorithm within the VI. The VI should be open access so you could modify to fit your needs.

I hope this helps point you in the right direction!

[johnsoja]

Thanks David.  Your response gives me enough info to at least develop a near term work-around.  I'm still waiting on a a response from a NI App Engr as well.

Joel

[ikelli]

Hi Joel, 

Unfortunately we do not have a lot of documentation about the Discrete Transfer Function Direct VI.  I have taken a look at what David posted and it seems like this is indeed likely due to the FPGA capabilities of fixed-point data types.  I would double check your models and then look more into David's posts.