Discrete Normalized Integrator VI in FPGA Not Working

[meeeeeeh]

Hello,

Attached is a screenshot of the frontpanel and block diagram of the VI I am currently working with.

The top section generates a sine and cosine wave with programmable amplitude and frequency set in the front panel.

The bottom section is supposed to mix the incoming signal with the cos/sin and then integrate.

At the moment I am only doing a sine mix and then integrating it.

I have put the output of the result of input mixed with sinusoid onto AO2 and seen it works. However, if I add the digital integrator after the output of input mixed with sinusoid then AO2 saturates to 500mV.

So I figure the Discrete Normalized Integrator VI seems to be overflowing.

According to its website:

http://zone.ni.com/reference/en-XX/help/371599K-01/lvfpga/discrete_normalized_integrator/  

the output overflow is a function of the input. So I have set a very large range on the input (the FXP cast after the mixing), yet the output still overflows.

Any ideas how to fix this would be appreciated.

I ideally want to mix the input with a sine and cosine, do an integrator on each result, then combine them (L2 norm) for a full coherent demodulation. 

[apriltalksrobots]

meeeeeeh,

It does seem like the Discrete Normalized Integrator VI is overflowing. On that webpage you linked, it says that the maximum input word length is 32 bits; have you exceeded this?

You could also try wiring a constant of the expected input to the input of the Discrete Normalized Integrator VI in case there is something off about the formatting of the input data.

What values are you expecting as an output?

-aprillest

[meeeeeeh]

Hello thanks for the reply.

Yes, the input is <32 bits. I have it set to 25 bits with 16bits fractional width  (range +- 32k).

I just wired a constant directly into it and it still overflows.

The constant is 25bit (16bit frac) input    and the output of the integrator is   41bit (32 bit frac).

 I then cast that output to single point precision float and then cast that to   20bit (5bit frac) before wiring it to AO2.   

(note: 20bit 5frac seems to be what AO requires for my board so its not the issue but perhaps a cast beforehand is).

[apriltalksrobots]

Can you try placing indicators after the DNI VI, as well as after the conversion to single-point and after converting back to a fixed point? This way we can ensure the value is being converted correctly. If you could post a screenshot this, that'd be great. 

You could also post this VI, so people looking at the thread could try to run it themselves. 

-aprillest

[meeeeeeh]

Hello thankyou for your help again.

Attached is the VI and a screenshot of the system after running.

Firstly, in the screenshot, you can see Numeric B and C have the same values showing the cast is working. They show a saturation at ~ -2^19 so I believe the integrator is just building up over time.

Numeric D is then saturating at -16 since its only 20bit (15 frac, 5 exponent).

Numeric A, the data before integrating, is however is showing the correct range of numbers.

I think the problem comes back to the Discrete Integrators VI definition: "the VI assumes that the integration interval (dt) is normalized to 1"    (ref: http://zone.ni.com/reference/en-XX/help/371599G-01/lvfpga/discrete_normalized_integrator/), so perhaps on each clock cycle it is integrating since I have not controlled its interval.

I want Euler integration every 4 cycles of the input (which is actually 1000 clock cycles  i.e.  40 MHz /  4x10kHz).

I was playing around with trying to control the speed of the integrator, but had no luck. I tried a while loop with a timing clock for control but that didn't work. I tried a for loop but then the integrator was outputing an array instead of a number.

Any tips / help are appreciated!

[WillD · Accepted solution]

If you really want to use the Express VI integrator you should be able to just multiply your input value by your dt before you pass it to the integrator.  I haven't tested this.

Or just implement your own integration, it is just a register, adder, and a multiply.

 

[meeeeeeh]

Thankyou I think I am close to solving my problem.

My last issue is that while the for loop runs for integration, nothing else runs.

This creates two problems: the output of my DDS becomes quite slowed down (blocky) and also I can not run another integration in parallel.

I want to perform the integral of   input x cosine   and   input x sine   for 1000ticks and run these in parallel. If I put the two integrations into the one for loop, then my loop output becomes an array but I can only have one output.

Is there a way to make sure I can run the integration loops in parallel and also make sure they aren't interfering with the DDS?

Thankyou

[apriltalksrobots]

Have you heard of flat sequence structures? They can be used to structure the flow of the program. I've included a link about them below. Do you think these would work for your application? 

http://zone.ni.com/reference/en-XX/help/371361J-01/glang/flat_sequence/ 

[meeeeeeh]

Hello,

Although this is an FPGA design, the designs seem to not be parallel which is odd.

If I run a FOR loop in a flat sequence to integrate, it appears to stop the DDS from working in the background in parallel until the FOR loop is finished.

Also, I can't  get it to run TWO integral FOR loops in parallel at the same time. Flat sequences will make the looping actions sequential.

[apriltalksrobots]

meeeeeeh, 

First, I was looking back at your original attachment, and realized that you had two Loop Timers in one While Loop. You should only use one Loop Timer per loop to make sure they aren't interfering with each other. 

Second, how do you know the For loops aren't running in parallel? Are you using Highlight Execution? Highlight Execution may show them happening sequentially when they are in fact operating in parallel. 

If you could attach a screenshot of your updated code, that would be very helpful! 

-aprillest