LabVIEW

cancel
Showing results for 
Search instead for 
Did you mean: 

Digital Data Reading

Hello,

I'm using NI development kit including the FPGA single board rio sbRIO-9651, I want to know about the data acquisitation method. My ADC is converting signals from the CMOS sensor (3 channels red,green & blue) to digital and now I want to read this 16 bits digital output data in LabView for further processing. CMOS data output format is shown in the diagram and I need to read and save this data in the same sequence.  Any idea how I can achieve this?

 

0 Kudos
Message 1 of 10
(3,817 Views)

Hi AhmerKhan,

 

you need to check your CLK input for edges (falling/rising), then you wait for a certain amount of time (which is not indicated in your image), then you read your digital inputs…

 

What's your problem? Where are you stuck?

Show your current VI (attempt)!

Best regards,
GerdW


using LV2016/2019/2021 on Win10/11+cRIO, TestStand2016/2019
0 Kudos
Message 2 of 10
(3,772 Views)

Hi Gerd W,

I haven't tried to construct IV yet cuz I don't know from where should äääi start as I'm a newbie in the LabVIEW. It would be great if you help me.

I'm getting a 16 bit data on falling and rising edges of the clock and the clock frequency is 3MHz. I need to collect and save the data in the same sequence.  

0 Kudos
Message 3 of 10
(3,768 Views)

Hi Ahmer,

 

cuz I don't know from where should äääi start as I'm a newbie in the LabVIEW.

When you are new to LabVIEW you should start with all those FREE online resources offered by NI for LabVIEW beginners! Learn LabVIEW (in general) first, then learn the specialties of LabVIEW Realtime, then learn the specialties for LabVIEW FPGA - you will need all this!

After all this you should study all those example VIs coming with LabVIEW…

 

And please read this!

Best regards,
GerdW


using LV2016/2019/2021 on Win10/11+cRIO, TestStand2016/2019
Message 4 of 10
(3,762 Views)

Hello I have attached a block diagram of my VI, I want to know how can I save the data coming from my ADC on rising and falling edges. In this VII have tried to see the data with the clock falling edge data but its also not working. Can you please guide me how can I capture double rate data and save it as an integer value. My output data format is shown in diagram.

Thank you 

Download All
0 Kudos
Message 5 of 10
(3,726 Views)

Hello, AhmerKhan, welcome to LabVIEW.  As GerdW pointed out, you have quite a learning experience in front of you -- LabVIEW (a month or so, at a minimum), Real-Time (ditto), and FPGA (a piece of cake once you've mastered the other two ...).  If you really want to make rapid progress, find a LabVIEW Guru who will be very critical of your code, learn good LabVIEW Habits and Style (there are some good books, including "The LabVIEW Style Book", by Peter Blume), and write lots of code.

 

Speaking of which -- if I were asking you for help with a Matlab or C++ program, would you want me to send you a PNG of 400 lines of code?  You'd want the m-file or the C source.  Well, in the LabVIEW world, code is the .VI, not a picture of the code.  Attach your code.

 

Bob Schor

0 Kudos
Message 6 of 10
(3,718 Views)

What Gred Gerd has stated is a good start but "the devil is in the details" (Ross Peroe)

 

A couple of sugestions that may help you get started...

 

1) Concentrate on a single data line along with the clock. You can easily add the other lines once you know what will be required.

2) Keep track of the the sate of the clock between iterations (using afeedback node). When the clock transistions (exclusive NOR gate) read the state of the data line and update the proper value (line 0 vs line 😎 depending on which way the clock transitioned.

3) An ASR (artihmetic shift left ) can be used to set the data bit.

4) Faster sampling will let you control the delay time between the clock transitions and the data line is sampled. If you can sample faster enough there a "debounce" functions included in FPGA so you may want try those to make sure you are reading the proper value from the data line.

 

Have fun!

 

Ben 

 

 

 

Retired Senior Automation Systems Architect with Data Science Automation LabVIEW Champion Knight of NI and Prepper LinkedIn Profile YouTube Channel
0 Kudos
Message 7 of 10
(3,686 Views)

Hi Ben,

For iteration there are around 1190 clocks to get a complete pixels data from 16 bits ADC 8 output ports, can you please explain it in more detail that how can I track the status of the clock and save it on PC as a text file.

I have also attached my VI.

0 Kudos
Message 8 of 10
(3,660 Views)

@AhmerKhan wrote:

Hi Ben,

For iteration there are around 1190 clocks to get a complete pixels data from 16 bits ADC 8 output ports, can you please explain it in more detail that how can I track the status of the clock and save it on PC as a text file.

I have also attached my VI.


Hi AhmerKhan!

 

1)

What you wrote is an "elevator version" of a project specifiaction typical of the types of applications I develop to feed my family. I can only offer some thoughts and suggestions to help people over the rough spots. So you can not rely on me to get you to the end of this challenge.

 

2)

I do not have LV 2016 on my machine yet (just dilvered a year long project that started with 2014) so back-saving your VI for 2014 or 2015 will get you more veiwers.

 

3)

Your task as outlined is not trivial. Take it step by step, shar your code as you go, keep your questions focused and the team here on teh LabVIEW forum may be abel to get you where you need to go.

 

Trying to help,

 

Ben

Retired Senior Automation Systems Architect with Data Science Automation LabVIEW Champion Knight of NI and Prepper LinkedIn Profile YouTube Channel
0 Kudos
Message 9 of 10
(3,646 Views)

Hi,

I have build a VI to detect rising and falling edge of my 9 MHz clock and read the data on these edges. I have complile a VI to in FPGA target to detect and clock and acqiire the data when the consition is TRUE and sent the data to Host PC via FIFO. But its not working and idea how can I solve this problem. Currently my output clock is 9MHz and the data format is like I should get high on rising edge and low on falling egde. I'm using SCTL clock at 18MHz but I'm getting high-low sequence data on both the edges 😞

Any help or suggestions would be appreciate.   

0 Kudos
Message 10 of 10
(3,558 Views)