05-20-2013 12:57 PM
Hi , as part of my project I shall take Manchester coded data and decode it. 1/2 bit low 1/2 bit high is decoded as 0 and 1/2 bit high 1/2 bit low is decoded as 1. Sync is also invalid manchester pattern of 1 1/2 bit high and 1 1/2 bit low. Attached picture can shows an example of sync bits+data bits
I know how to decode the code but my problem is timing. The sync pulse is created by FPGA through FIFO. Can you show me how can I extract the invalid sync bits and start decoding when the sync pu;se triggers in LabVIEW
many thanks
05-20-2013 01:18 PM
Are you trying to do the decode in the FPGA or in the host? It is a lot more efficient to do this decode in the FPGA.
It is a lot easier to look at this as each data bit is 2 transmit bits. So then your sync is actually 6 bits long (3 bits high and 3 bits low). And then your data bits are determined from 2 transmit bits from there (F, T = T; all others are F).