Data transfer possibilities between two FPGA VIs under one FPGA target with two VIs not being called from the other

[charansai]

Hello there,

I have been trying several things to accomplish the data transfer between two fpga VIs.

First I considered using target scoped memory, but I found target scoped memory will be initialized each time the working vi stops i.e essentially it will also work like VI scoped memory, only difference between both being taget scoped memory can be used in several instances(VIs), any changes made to these memories will essentially influence all instances, which is not the case for VI scoped.

I guess memory access is possible only over different clock cycles of the VI or between two VIs where one VI calls the other i.e one being the top level VI.

[1]

Then I thought Target scoped FIFOs will be the solution, but same is the case with these also.

[2]

Please correct me if I am wrong with these conclustions.

As I have to access sth like 128 elements from one VI to another VI, the registers and hand shakes are not the solution.

Another big problem that I found is, the DMA FIFO transfer does not work for sub VIs. I mean, if I am using LMS as subVI where filter coefficients will

get updated all the time but I am using the subVI LMS in another  top level VI. Now if I have to access coefficients from subVI using DMA FIFOs by running top level VI. It isn't working.

Again correct me if I am wrong .

Now how to do it, the data transfer between two FPGA VIs? Are there any specific techniques to accomplish this?

Thank you.

[Sam_Sharp]

There is a good reference about the different methods for sharing data on FPGAs here: http://zone.ni.com/reference/en-XX/help/371599G-01/lvfpgaconcepts/fpga_transfer_data/

You can also create Global Variables on the FPGA - I've used one in a recent project for sharing a 64-bit tick count between loops. Oh, I think you can also use FGVs (functional globals) on FPGA, too - but there may be limitations around having non-reentrant VIs and probably won't work in single cycle timed loops.

[nathand]

Please stop creating so many threads for what is essentially the same question (it is good, though, that you linked to the previous threads). Also, what is "sth" and why do you use it all over your messages?

Despite reading through the messages in all three of these threads, I cannot understand what you are trying to do. If you will stop the FPGA and restart it (or start a different FPGA VI), you need to transfer the data to the host, as there is no mechanism that I know of guaranteed to preserve data on the FPGA between executions. There is no problem using a DMA FIFO inside an FPGA subvi, though. Can you be more clear about how it "isn't working"? When you compile a top-level FPGA VI, the entire hierarchy (all subVIs) are effectively flattened into a single large diagram, so there is little difference between putting code in the FPGA top-level versus in a subVI (with certain exceptions, particularly if arbitration of a shared resource is required).

[charansai]

Hi,

Thanks for the reply 🙂

sth- some thing 😄

First of all pardon my terminology, I am quite new to LabVIEW

Its not my intention to create many threads instead I have been trying many things. As I am very new to labVIEW and labVIEW FPGA I am struggling a lot to understand many things. ! Initially I thought "Target scoped memory" is the solution, then I found about "Target scoped FIFO". Now I am getting feeling that it is impossible to transfer data between two independent FPGA VIs under one target.

Anyway about subVIs DMA Transfer, 

I tried putting DMA FIFO at marked position, and I used this entire FXP LMS code as a subVI in another FPGA VI(main VI). Now I run the FPGA VI along with Host VI to read the coefficient and it is not giving any results. This is one problem !

Another main problem is I want to use these LMS adapted 128 coefficients from this main VI in another complete independent VI . This independent VI is not in hierarchy with the main VI in anyway. Is it possible to do this ??

Can you explain the little difference between putting code in the FPGA top level vs in a subVI? ( any reference is much appreciated. )

Finally, I guess I have to upload my entire project to explain my problem clearly. I will do that tomorrow.

Thank you.

[nathand]

You cannot run more than one top-level VI on the FPGA at a time, so you'll never have two totally independent VIs running in parallel on the FPGA. Those two VIs will have to be started from the same top-level VI and compiled into a single bitfile. I'm confused about why you want to transfer data between "independent" FPGA VIs.