Data storing using FPGA and RT targets

[mhran1985]

Hello everyone

I am doing a project based on using NI CompactRio FPGA, my program has been done on the FPGA target and it is working very well, but I have a problem. I would like to save my results, I have used RT target to send the data there through FIFO block, but because I have a huge data, I am trying to find a method to reduce my sampling time just in RT target.


The whole program on FPGA target is running at sampling time of 40 us to estimate the SOC of 24 battery cells, the cells have different SOCs, so I have to measure all the SOCs and I want to run the program for 1500 sec continuously, this means I want to save ((1500s/40 us)*24=900000000 data) and this number is very big, I am looking for a way to reduce the number of saved data in TDMS file by decreasing the acquired sampling rate just in RT target to make it for example (1 ms instead of 40 us) without changing the sampling time in FPGA target because I need to do the calculation there based on 40 us sampling time.

Can anybody help me to know how to change the acquire sampling rate just in RT target without changing my program on FPGA target?

Mahran

Can anybodey help me to know how to change the acquire sampling rate just in RT target withouth changing my prgram on FPGA target?

Mahran

[nathand]

How are you transferring data from the FPGA to the RT host? If you're using a DMA FIFO, an easy solution is to maintain a counter in the FPGA code. When the counter is at 0, write the data to DMA FIFO. Increment the counter on each loop iteration, and when you reach the desired count, reset to 0. So if you only want to transfer one out of every hundred measurements to the RT host, count from 0 to 99, then reset to 0 and transfer the next data.

[mhran1985]

Hi Nathand

Thank you for your help.

Yes I am using DMA FIFO.

I understand what you mean, If I want to transfer one out of every 100 measurements to the RT host, I have to use counter. But the problem is the RT sampling time corresponds to the Count(uSec) control on the FPGA VI front panel, I mean if you run the program, the RT still acquire data from FIFO based on the same sampling time of FPGA target?

[nathand]

If you are using a DMA FIFO to transfer data (and you might not be), then the RT host only reads the data that was put into the FIFO.

Please upload or attach a screenshot of your code; that will make it much easier to have a discussion about it.

[mhran1985]

In fact my code is saved on my computer at the university and I do not have it now, tomorrow I will attache it here.

consider that I want to send 1 value/ 100 values calculated by the FPGA target based on using the counter as you suggested and the sampling time is 40 us

 the 1st 100 values, the RT target acquires the one value, let me call it (x)

 the 2nd 100 values, the RT target acquires another one value (y)

in this case, do you think the time between x and y is 100*40us=4ms??

[nathand]

I would like to see your code before commenting, because I'm concerned that there may be a misunderstanding here and I don't want to create confusion by saying yes to something you write, then finding out that it doesn't match your code.

In a typical architecture, the FPGA would read from the input at a regular interval (say 40us) and write those values to the DMA FIFO one at a time. The RT host reads multiple values - say 1000 - at a time. Those 1000 values represent 40us * 1000 = 40ms of data. If you want the sampling rate on the host to be 4ms instead of 40us, then you would modify the FPGA so that it only writes one out of every 100 samples to the DMA FIFO. Or, you can leave the FPGA code as is, and read 100 samples at a time from the DMA FIFO but only log the first one and discard the rest.

[mhran1985]

My code in RT target is similar to that.

[mhran1985]

I sent the data to FIFO exactly like this FPGA target code, the only difference is I have 24 channels connected to the array instead of 4

[nathand]

In that case, yes, my suggestion applies. Put a case structure around the For loop. Add a shift register around the while loop to act as the counter. Increment the counter on each while loop iteration and reset to 0 when it reaches whatever value you want. Put the For loop inside the case that resets the counter to 0, and then you only two cases: Default case that adds 1 to the counter, and the case that resets the counter to 0 and sends the data.

(I often implement this as a count-down instead of a count-up, with the logic in the 0 case, but that's personal preference.)

[mhran1985]

Thank you very much. I will try to do what you said tomorrow and tell you what happens with me

Thanks again

by the way, my name is Mahran and I live in Birmingham- UK

Nice to talk with you

Regards