Data channel switch in FPGA application

[zwfjames]

Hi, I add your quotient & Remainder selection to " the number of elements to read ". I found the channel constantly switched to the previous one ( like AI1 goes to AI0), even if I connected the right channel in hardware. So I can now save the data as it switched and do the post processing later. However, I still have no idea why it becomes switched.  The problem was solved in an unexpected way. But I really apreciate your help! Thank you1

[zwfjames]

yes you are right!

[bjoa]

Jeff·Þ·Bohrer

Try it as a mental exercise, if you have 8 channels and build the data in array (FPGA only concatenate the data) you've the following array: 1-2-3-4-5-6-7-8-1-2-3-4-5-6-7-8... (according to the number of channels), if you read a number of elements that isn't divisable by 8, for example 10 elements, you will read: 1-2-3-4-5-6-7-8-1-2 and leaving 3-4-5-6-7-8-1-2-3-4-5-6-7-8... the next you will start read the channel 3, that is not correct.

[bjoa]

Actually I've the same problem, in the RT side when I plot them they shift one position, for example: I see the data of channel 1 in graph for channel 2, etc.

[JÞB]

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@bjoa wrote:

@JÞB

Try it as a mental exercise, if you have 8 channels and build the data in array (FPGA only concatenate the data) you've the following array: 1-2-3-4-5-6-7-8-1-2-3-4-5-6-7-8... (according to the number of channels), if you read a number of elements that isn't divisable by 8, for example 10 elements, you will read: 1-2-3-4-5-6-7-8-1-2 and leaving 3-4-5-6-7-8-1-2-3-4-5-6-7-8... the next you will start read the channel 3, that is not correct.

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That's not what I was pointing out.  Certainly, I understand taking N Chan number of samples out of a buffer.  Quotient and remainder is your friend in that!  

I merely pointed out the ridiculousness of changing the logic when the remainder is zero.  Work it through as a mental exercize  samples avaiable - 0 is equal to samples available minus remainder ONLY when Remainder = 0 and both inputs to select are equall to each other!  The selection criterea is Remainder Not equal to 0.   

So just read samples available  minus samples available mod n remainder

[zeze07]

Hi all,

I had the same problem, and was able to solve it this morning thanks to the Labview engineers. I added the FIFO reset to my software on the host side and it has stopped the channel switching errors. Because the FIFO Reset does not work in simulation mode, I removed it a long time ago, and therefore forgot to add the Reset when it was time to execute on the target. The Reset worked for me, so just add it in once you are ready to execute your software on the FPGA target. I hope it works! I have attached two images on how to set up the Host and Target DMAs, and also how to clear the FIFO using FIFO reset. 

These VIs were provided by tech support! Also, the software seemed to stop switching when using the case structure on the host side (see pictures); I found that the software did not stop the channel switching with the remainder technique.

Zee

[bjoa]

Jeff·Þ·Bohrer

Got it, I didn't see your point, you are right.

[JÞB]

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@bjoa wrote:

@JÞB

Got it, I didn't see your point, you are right.

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It happens that occasionally I am right,  It usually supprises my wife too when that happens