DMA FIFO and VHDL Node

[Afghow]

Hi guys !

I'm posting here after a lot of days of attemps without success...

My application is "simple", some data are sending from the Labview RT front panel inside a Host to Target DMA FIFO. Then the FPGA Core receives the data and process it through an imported VHDL Node, and then after the data is sending back to the Labview RT through a Target to Host DMA FIFO.

I've tested my VHDL Node in simulation mode within Labview FPGA where data were sending through a Target scoped FIFO and everything just work fine.

But when I'm trying to run the VHDL Node in the real target with data coming from the RT Core through DMA FIFO, it goes wrong. I've already make some verifications :

- Data are sent correctly through the Host to Target DMA FIFO;

- Data are received correctly in the FPGA Core;

- Data are correclty sent to the VHDL Node;

- Result of the VHDL Node are correclty sent the RT Core through the Target to Host DMA FIFO;

- Result are correcly received in the RT Core, but the result is wrong and absurd. But I've have the proof that my node is semanticly correct with my simulation test.

So my question: is there some reasons to see my VHDL Node working nice in simulation mode and not in real target mode with data from the RT Core through DMA FIFO taking account data transfert between DMA FIFO are working well in both side ? Is there some sample available with data sending from RT to FPGA Core through DMA and data processing with a VHDL Node and sent back to the RT Core to inspire me ?

I can't post my VIs here because I'm working for a company, I'm using a MyRIO Target with Labview FPGA 2014.

Thank you guys ! I'm available for some details about my implementations.

Afghow.

[Afghow]

No advice/solution ? 😕

[speleato]

Hey Afghow,

There shouldn't be anything special about the DMA FIFOs with a VHDL node. Whatever you put in one side should come out the other side, regarldess of the source of the data.

One question I have for you, when you say that the data is correctly recieved and/or sent, do you mean that some data has moved or are you able to verify that the data has the correct value at each intermediate point. I think the key to figuring this out is to find out exactly where in the process the data becomes wrong and absurd.

Are you able to write a simple set of VIs that reproduces the issue? Perhaps one thing to try would be to keep the DMA FIFOs but remove the VHDL node. The simpler the reproducing case, the easier it's going to be to get to the bottom of this.

Sebastian

[Afghow · Accepted solution]

Hey !

Thank you for your reply but I have solved my problem. Indeed, in a first time I tried to make a pure combinatorial (without clock) node but the problem seemed to come from that.

I've modified my node to integrate a clock, following requirements of this white paper : http://zone.ni.com/reference/en-XX/help/371599K-01/lvfpgaconcepts/ipin_prepare_ip/ . And now every thing seems to work well.

The question stays why the combinatorial node worked in simulation mode en not in the real target ?...

But for people with the same problem I suggest them to add a CLK input and check an input edge with rising_edge(CLK) and if it's not working, add an input signal to check if input signals are valid or not.

Afghow.