Crio_9024: FPGA compilation error_resource overmapping_DSP48s 114.6% used

[Ali_H]

Hello,

I am using labview 2013 with CRIO-9024

I have a problem with my labview FPGA compiler where it brings up an error at the mapping stage due to resource overmapping. The issue is shown as DSP48s 114.6%  of total 48. I am not familiar with this term as I have only used FPGA with labview. However from what I gathered through reading other discussions that there is a way to force the complier to use more of the LUT slices and other slice registers if the DSP48s is full. note that my slice LUTs are at 30% and my slice registers are at 22% for the VI that i am trying to compile. 

I am not sure why this is happening on my machine although the code is not that big, and it is the first time that it happens. 

I would appreciate any help. 

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Kind Regards

Ali

[r_good]

We would need to see the vi to help offer input on how to optimize your resource usage.  Be careful with complex math operations and high throughput fized point math as they can eat up DSP48's.  Please post the VI for further assistance, the log will not help us offer advice on resource usage.

[Ali_H]

Hello A_Tish,

Thanks for your reply. herewith the code i am trying to compile on the fpga. The bit that i find annoying is that the code is eating the DSP48s but keeping the slice LUT and registers at low consumption.

just a brief description of what the code does:

Reads 4 input signals: two acceleration signals. One voltage signal. one Current signal. 

the whole idea of the application is to reduce the acceleration of a particular mass using an actuator that is driven by a power amplifier fed from the PID output in the code. the PID generates the required voltage to the power amplifier based on comparing two current signals, a reference and the actual one of the actuator.

if you need further information about the code, please let me knoe.

I just have to note that this code run on nimyrio perfectly without a problem. so the assumption is that it should compile without a problem on a compact rio.

Kind Regards

Ali

[r_good]

I am out of town but will check the VI out.  The myRIO from what I recall, uses the new Kintex family which is quite large.  There is a chance that the new crio FPGA is smaller but I wlll check that out as some point today and see if I cannot help.

Good luck in the meantime while the community reviews and tries to help.

[Ali_H]

Thanks for your response. Actually I have managed to figure out what my problem was. I can confirm it is not a Labview/Xilinx compiler bug. I actually was using a block that was eating up most of the DSP48s. But many thanks for your help. 

[LiPo_xmu]

Hello Ali_H,
I am using labview 2013 with RIO0-7851R, and I met the same problem, that is the code is eating the DSP48s but keeping the slice LUT and registers at low consumption.
I look for help but didn't solve my problem.
Do you find the way to force the complier to use more of the LUT slices and other slice registers if the DSP48s is full?
Looking forward to your reply.

Kind Regards
LiPo

[Jacobson-ni]

If you can, it would probably be best to start your own thread and post the application you are trying to compile. Getting the compiler to use more of one resource over another usually involves figuring out what is using the majority of the specific resource you are trying to minimize and replacing it with something that has comparible functionality but uses different resources or optimizing algorithms to use less.

A_Tish posted some really good general advice but like they mentioned, we can't do much more without code.