Creating an SSI bursted pulse-train TTL clock with hardware timing using cDAQ NI 9401

[RyanBiggs]

Hello all!

As part of a complex project, I must implement an acquisition hardware interface for a linear motion sensor using the Synchronous Serial Interface (SSI) output common in industrial motion control.

To do this, I need to create a hardware-timed bursted pulse train TTL clock signal. Each burst consists of 25 high-low transitions with a full-cycle period of 2.67 microseconds (375kHz).  The output must then be held high until the next burst, which occur at 1ms intervals.

LabVIEW support tells me this can be achieved using a NI 9401 cDAQ module and the clocks on a cDAQ chassis. Can any of you folks suggest the appropriate VIs and/or general strategy for this?

This is step 1. Step 2 will be reading the data clocked out of the sensor by this clock signal using an NI 9411.

Thanks for any pointers!

[Dennis_Knutson]

Have you looked at https://decibel.ni.com/content/docs/DOC-1095?

[RyanBiggs]

Thanks Dennis,

It seems the example files are missing some dependencies, but I'll look into it further. However, since we don't have a real-time/FPGA/cRIO system but just cDAQ, I'm not sure if that topic is relevant or not. According to NI, either the FPGA approach descibed or the DAQ timer-based one I am looking for should work.