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Converting ADC digital value on FGPA

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Hey guys,

 

I have an ADC7690

AD7690.PNG

Please note, that I am using 2.5V as Vref so the max/min analog input values and LSBs are half the voltage.

 

Now I have the 18bits from the ADC in a FXP I18.1 format on my FPGA and I want to do some further signal processing with it. Later on I want to display my result (of the signal processing) on my computer and I have to "scale" my value. The gains from the signal processing are already calculated and the result is multiplied with it which gives me correct values. Only the ADC scaling is missing.

Is it correct, that I only have to multiply the result with the LSB (19,08µV) and 2^17 (to get from I18.1 to I18.18) ?

 

Signal processing:

- Multiplying my ADC signal with a sine/cosine of the same frequency (ADC signal is a noisy sine) = Demodulation

- Lowpass filter and downsampling: CIC filter followed by moving average or exponentially weighted moving average

 

 

kind regards

Slev1n

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Solution
Accepted by topic author Slev1n

Hello Slev1n,

 

If you want to display your results, it means that you are no longer on the FPGA. So, it would be much simpler to convert your fixed point to a DBL and then do the engineering scaling.

 

Michel

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Hi Slev1n,

 

even though you are using half input range of the ADC, you have to multiply the value you are acquiring with 38,15 uV and to divide by 2^18.

However, it is better to make these computations at RT or Host level, since they require too much resources in FPGA and they could heavly slow down your application.

 

Hope my answer will help you.

 

Kind regards

 

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Hey guys,

 

yes, you are both right. Of course I am going to make the calculations on the Host site. I have been thinking since posting my question and it is as I thought:

 

Signal --> System --> Signal*gain. So my signal goes into my "Filter System", afterwards I still have my signal times a certain gain. So it doesnt matter if I convert my signal before entering the system or afterwards when I have compensated the gain. Except for what you have mentioned, that I wont be using ressources on the FPGA which I dont have anymore on myRIO 😄

 

kind regards and thanks for your help

 

Slev1n

 

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