Coding Architecture

[meBaga]

Hi, I’m looking for some architectural solution,

I am using FPGA to acquire a signal at a sample rate of 10 kHz. I want to send this signal to RT and calculate the Fundamental signal of that (using 5 consecutive cycles) then send that Fundamental signal back to the FPGA as a reference(1 full cycle).

So Next time onwards, This FPGA VI will take each sample and subtract with the reference signal and give us the deviation amount.

Suppose we have a 50 Hz signal, so number of sample in 1 full cycle will be 200. So while crossing 0(negative-to positive) the input signal will compare itself with the 0^th element of the reference signal. Next time onwards … every element will compare itself with the next element of the signal. Till the next zero crossing (negative-to positive) this will continue expected as 199^th element. Then again it will compare itself with the starting element when it will get the zero crossing.

The reference signal will keep on updating by the RT depending upon the last 5 cycles.

Now give me some idea by which I can implement it using DMA FIFOs.

[Bob_Schor]

This is not a LabVIEW-for-Hire Forum, it is a place to get help with LabVIEW.  Post your efforts, tell us where you are stuck, and we will help.

BS

[Jacobson-ni]

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@meBaga wrote:

The reference signal will keep on updating by the RT depending upon the last 5 cycles.

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Remember that data communications to and from RT are not deterministic.  If you want to compare one period to the previous five you will need to send up your previous period (previous 4 will still be there), calculate reference, then send it down in time to compare it to your current readings.  

If you are doing a simple average I would suggest keeping it to the FPGA.

I think the hardest part of this will be breaking your continuous input signal into cycles of the same length. Real world signals have a tendency of making things messy.

[meBaga]

Presently I am using DMA FIFO to send the signal to the RT. In RT I'm reading 1000 samples at a time in RT, converting it to waveform type, calculating the fundamental frequency and amplitude. Generating a signal with 200 number of sample, then get the raw value data and sending it back to RT using DMA FIFO. 

In FPGA I'm using a 200 block memory and storing the latest data comming from RT into that.

Then while crossing 0 (From negative to positive) I'm compairing it with the 0th element of the memory, and next values .... +1 .... 

Data transfer to/from RT will not be deretministic, I understand that. If I'm allowed to ignore that much error, then is the process ok ??