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Close FPGA Hold Line States

Hello, I'm using LV2011 with the FPGA module. I'd like to do a simple program that sets the states of 4 digital lines on the FPGA and keeps those states after I close the FPGA reference on the host computer. Is this possible?

 

Thanks,

Ed

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Hey Ed,

Once you set the state of a line from the FPGA, it will remain set to that until you either tell it to change to something else, or until you reset the device.

 

The FPGA's hardware and transistor configuration that is pushing a line, in this case 4 digital output lines, to a given state need the inputs to change before the logic gate structure changes.  By closing the FPGA reference, you stop modifying the inputs.  Additionally, resetting the device also changes the inputs.

 

In short, if you set the lines then close the reference, the lines will stay high until something tells them to be something else.  I hope this answers your question!

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