Clock input simulation for FPGA

[OregonGumby]

I am using PXI-7841R FPGA module in simulation mode.  I would like to verify and troubleshoot my code on the PC before downloading it to the target.  I have my project in simulation mode and it runs fine but It seems like that the input signal from the clock input is  randomly generated.  Is there a way to specify that data coming in?  I am trying to simulate rs422 which uses an external clock to sync the data output.  I want to simulate that clock.

[James_McN · Accepted solution]

If it is an IO point there are only two options open to you:

• Use a conditional disable to run different code in simulation mode - effectively write a clock generator in simulation mode.
• Try the FPGA desktop execution node - This is hugely powerful and allows you to run time based simulation from the desktop but does take a little more setting up.

Cheers,

James