I have an FPGA project with two identical host to target FIFOs. (I have checked many times the settings on the FPGA side are identical in all but name).
Problem is, one of them is functioning as expected and the other is not.
In the FPGA FIFO project items, both FIFOs are configured as 1029 elements (coerced from requested 1023, which is fine).
When I call FIFO.configure from a PC side property node to set the PC side FIFO memory (this is a DMA FIFO), one FIFO reports an allocated depth of around 100000 as requested (and can be set to 10x this if I choose), whereas the other reports zero elements.
When invoking FIFO.write from the PC, sending a zero element array (for the purpose only of querying the 'empty elements remaining' output this returns, the working FIFO returns the expected 100,000 whereas the other reports 16,384.
I have tried configuring these FIFOs in reverse order and the result is the same- it is that same FIFO that is not responding as expected, regardless of initialisation order.
This is on a PXI-5644R VST if it makes any odds.
Any ideas regarding the differences?
