Boolean shift registers in FPGA not working as expected in LabVIEW 2012

[MJ]

I realize this issue is LabVIEW version dependent since the same exact code works perfectly in LabVIEW 8.6 for me.  Is this issue only associate with LabVIEW 2012 or FPGA 12.0?  What would be a work around for this issue?

[nathand]

Are you using multiple copies of this subVI in your FPGA? VIs created under an FPGA target are set to preallocated clones shared execution by default. VIs created under other targets are not reentrant by default. If you created a similar VI on the system that has the FPGA tools installed and it worked, but then wrote this one on a non-FPGA target and moved it to an FPGA without changing the reentrancy settings, and you call it in multiple locations, that could also explain the problem.

If it really is an issue with one specific version of LabVIEW, try replacing the shift registers with feedback nodes. It seems highly unlikely to me that there's a problem with shift registers on FPGA in one particular older version of LabVIEW, though.

[MJ]

Thanks Nathad, it is a good pointer, I will look into the reentrant settings.  It is not supposed to be a reentrant VI, and it is called from only one place.  I will have to make sure its caller is not a reentrant VI.

[Dragis]

The originally attached VI is marked as non-reentrant, so it would be good to check that there is only one caller if that's a necessary constraint.

I put together a small testbench and ran it in 2015 and the FPGA and Desktop match execution behavior. Can you run this testbench in 2012 (which I don't have installed) and see if the results are different.

[MJ]

Thanks for your reply and suggestion.  It did not solve my issue.  Perhaps, my issue is only an issue in LabVIEW FPGA 2012 and not applicable for other versions.

All my FPGA VI's are non-reentrant and my problematic VI is called by one other VI.  

Instead of using non-initialized shift registers to store the boolean states from the previous calls, I worked around my issue by using a physical memory slot defined in the FPGA environment.  I would read the memory slot (similar to a global variable in FPGA) for the previous boolean states at the start of the VI and store the new states to the memory slot before exiting the VI.  This work around solve my issue.

[Dragis]

Thanks for the update, @MJ. I'm glad you were able to find a solution to your problem. Just to be clear, you tried the testbench I attached above and it fails in your install of LabVIEW and LabVIEW FPGA? If so, I'd like to track that issue.

[MJ]

No, I did not try your testbench.  But I am sure non-initialized shift registers do not store the previous boolean states correctly for me when using LabVIEW FPGA 2012.  The readback from the non-initialized shift registers at the start of my VI are always TRUE, regardless of the previous recorded states.