Boolean shift registers in FPGA not working as expected in LabVIEW 2012

[MJ]

I created a simple FPGA VI to set two DIO output pins based on the states of a input number and a shift register (see attached VI).  The VI was created using regular LabVIEW as the FPGA development module was installed on another computer.  In the FPGA version, the only difference in the VI is to replacing the two boolean indicators with DIO output resouces.

Consider running the attached VI in two steps:

1. Run the VI with input parameters: Operation=Set First Number; Number To Be Set=-5.

2. Run the VI again with input parameters: Operation=Set Second Number; Number To Be Set=-5.

Using regular LabVIEW, both boolean indicators showing the input numbers is negative all lit up after first step; then the first indicator stays on while second indicator is set to true after the second step as expected.

But in the compiled FPGA code, the shift register behaved incorrectly using LabVIEW 2012 FPGA module.  After the first step, first DIO outputs are set to high; after the second step the first DIO output is reset to low unexpectedly while second DIO output is set to high after the second step.

If we add one more step in the FPGA execution sequence:

3. Run the VI again with input parameters: Operation=Set First Number; Number To Be Set=-5.

Now the first DIO output is set to high but second DIO output is reset to low unexpectedly.

It appears that the boolean shift registers in the LabVIEW 2012 FPGA module only store the TRUE state.  Please note that the exact same FPGA VI works perfectly using LabVIEW 8.6 FPGA module.  The upgrade to LabVIEW 2012 broke this functionality.

Did someone run into this issue before? What might have caused this FPGA issue and what would be a good solution?

Thanks in advance.

[arevh]

The code attached is working correctly. Is that the correct one?

You are checking if the Number To Be Set is >=0, and then inverting the result. Of course the result will be TRUE if the number is -5.

During each iteration comparison result (FALSE) is written to the shift register, to be read for the next run. So in both shift registers you always keep False value.

Is it possible the before you were initiating the shift registers with TRUE value?

Thanks,

Arev

CTO | RAFA Solutions

[MJ]

The attached code works correctly in regular LabVIEW but not in FPGA.  I expect the shift registers to remember the state of the previous number to be set.  But in FPGA, the shift registers always return TRUE (they should have been set to FALSE from the previous iterations sing Number To Be Set >= 0 is always FALSE from previous iterations).

[Dragis]

Does this work properly in newer versions of LabVIEW?

It sounds like there might be an issue where the VI runs before the front panel values are successfully transferred to the FPGA. Are the results on first run equivalent to what is expected with the default values of the controls?

[MJ]

I did not try it on the newer version of LabVIEW.  It was meant to be used as a sub-VI being called from a higher level VI in my FPGA program.  The front values are not visible within the FPGA program, instead the output of the boolean indicators can be measured from the hardware DIO output pins.  This issue appears to be related to the readback from the shift registers which always are read as TRUE even after the previous calls had set them to be FALSE.

[nathand]

Can you share the VI that calls this one, and the host code that interfacts with the FPGA? If this is happening in a fast-running loop, you might have an issue where you can't set both Operation and Number To Be Set simultaneously, which could lead to unexpected results.

[MJ]

I don't have the FPGA module installation with me otherwise I would share all the FPGA code with you.  The Operation and Number to be set are input parameters wired in the host code and the two boolen indicator are the output parameters that would be wired to the DIO output pin resources on the FPGA on sbRIO-9606,

[nathand]

Is there something that tells the FPGA to wait until both Operation and Number To Be Set are both set? Otherwise, you're likely to have the situation where you set the Number, the FPGA loops with that new Number but the old Operation, then on a later loop cycle the Operation gets updated. This could lead to behavior like what you're describing.

[mateh]

I tried this in LV FPGA 14.0.1 and could not reproduce the issue.

[MJ]

In all cases (even when the two input parameters are not set at the same time) I do not expect the boolean indication to be set to FALSE.  But in the three calls I described in my initial message, the first boolean indication was unexpectedly set to FALSE after step #2, and second boolean indicator was unexpectedly set to FALSE after step #3.  The shift registers are not saving the indication state from the previous call to the sub-vi as expected in the FPGA environment.