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Best practice FPGA<->RT->Host Communication

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Hi,

 

I am still rather new to Labview and I have to implement a real-time control and logging application.

I am confused about the different ways to communicate data between the three execution levels and would like an experienced advice on this.
I need the following:
FPGA:

1a) Record analog data with some kHz resolution (2 channels)

1b) an edge (frequency) counter for one of those channels

1c) send this data to RT and Host

1d) Control 1 analog output

RT:

2a) read data from FPGA

2b) PID control using the FPGA data

2c) send results from PID to the analog output mentioned above (1d)

Host:

3a) Read and log the recorded data from RT,

3b) Manage PID controls

3c) Display the running processes


I know this is a classic example and I should be able to extract this from existing examples, but given my small experience and the complexity of the project and the quantity of different examples, I am confused about the best practice solution.

I have tried to implement DMA FIFOs, but I have to read them at both host and RT if i write them on the FPGA, so would I have to implement two, one from FPGA to RT and one RT to Host? Should I implement one for each data channel or one with a data cluster?
Id be gratefull for a recommendation of a communication protocol or even a corresponding example project.

Many thanks and regards,

 

Robin

P.S.: I am running Labview 2013SP1 with a cRIO9074

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Accepted by topic author Rengel

well I'll try to take a whack at least at a couple of questions.  For the DMA FIFO, I would just implement the FPGA to RT host DMA FIFO. For getting that data from RT  to your host (I assume the PC where you have the GUI program running) you could use a network stream which is basically designed for that sort of thing, streaming data over Ethernet.

 

Don't implement one DMA FIFO per channel, no need to do that. I think you can indeed define the DMA FIFO data type as a cluster and that would be prob easiest. To digress a bit you can do the FIFO is interleaved data of a simple data type (not a cluster)  defining your FIFO size as a number divisible by the number of channels, and do the read elements as a number which is a multiple if your number of channels. That way when you read the data you can be sure that you undo the interleaving and get the correct channels out. 

 

Oh and you might to the PID control on FPGA as well, the VIs are there to do it. That might simplify things a bit if it's simple PID.

 

Isn't there a project template for a real time application with FPGA? I would start there.

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Accepted by topic author Rengel

My first thought was to move the PID into the FPGA.  It will eliminate some of the communication needs and be more deterministic.  You can set your PID coefficients with FPGA front panel controls since they should rarely change.

 

For streaming the two channels to the RT, use a DMA FIFO.  I tend to combine the values into a single value to send into the DMA (read as fixed point, convert to U32, Join Number to make a U64, write to DMA).

 

For PC to RT, use either the STM library with TCP/IP or 2 Network Streams.  If going with the Network Stream, you will need to come up with a protocol for sending your data to the RT (so the RT knows what data you are sending it).  RT to PC should just be your data in the second Network Stream.

 


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Accepted by topic author Rengel

Hi Robin,

Initial thought, move PID to the FPGA so you can get rid of the following sequence: acquire data on FPGA, transfer to RT, PID control, send new AO value to FPGA, output on FPGA.

Use DMA to transfer data from FPGA to RT that then pass it on to the host application.

Stream data from RT to host through low-level TCP/IP or UDP or even better Simple TCP/IP Messaging Protocol (just search for STM) or make use of networked streams (not my fave though).

I believe you would benefit greatly by attending this course:

http://sine.ni.com/tacs/app/overview/p/ap/of/lang/en/pg/1/sn/n24:20873/id/3259/

Good luck with your project!

 

Regards,
Jimmie Adolph
Systems Engineering Manager, National Instruments Northern European Region

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Alright, so I definetely need a DMA from FPGA to RT and a different protocoll to send the data to the host computer from there.

Moving the PID to the FPGA would only save the transfer of its results from RT to FPGA(, correct?).
Thank all of you for your helpful advice!

I think I can figure it out from here.

Many regards,

 

Robin

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