Alternate between digital output and analog input

[JPROC]

Forgive me as I'm sure there is a simple answer to my problem but being realtively new to LabView I'm not sure how to proceed.

Using producer/consumer achitecture I'm trying to accomplish the following:

Producer

1. Close Relay
2. Read voltage

Consumer

1. Compare voltage to expected value and append true/false value to an array.

This will run 8 times then wait for user input via dialog box then run 8 times.

My question/problem is how do I set it up so the digital out and analog in are timed properly and I get one ai sample after each relay is closed?

Hardware used is cDAQ, (2) NI9481 & (1) NI9221

Attached is the vi that I've come up with so far and a schematic to illustrate the intended application.

Any help is greatly appreciated.

[mikeporter]

Don't have the input and output tasks in separate error chains.

I assume that the read goes where you have the 1 second delay, right? Move the ananlog read and enqueue operation there. The analog initialization and stop can be outside the producer loop. Also when enqueueing the data you probibly need to include some sort of value to tell the consumer loop which relay was closed.

The boolean output would alos be more efficient if you did port IO (no need to be constantly reinitializing the digital output) and define the bits in the port such that only one bit is on at a time durint the on phase and everything is off during the off phase.

Mike...

[JPROC]

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@mikeporter wrote:

Don't have the input and output tasks in separate error chains.

I assume that the read goes where you have the 1 second delay, right? Move the ananlog read and enqueue operation there. The analog initialization and stop can be outside the producer loop.

Yes, the read is intended to occur during the 1sec delay. Does the attached reflect your suggestion?

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@mikeporter wrote:

Don't have the input and output tasks in separate error chains.

Also when enqueueing the data you probibly need to include some sort of value to tell the consumer loop which relay was closed.

The boolean output would alos be more efficient if you did port IO (no need to be constantly reinitializing the digital output) and define the bits in the port such that only one bit is on at a time durint the on phase and everything is off during the off phase.

Mike...

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I'm not sure I'm following you on this.

[mikeporter]

For the most part, yes. But you are only going to get one sample sent to the consumer loop after all the relays have been toggled. Move the enqueue inside the loop right next to the analog read so the consumer loop will see all the reads. Do you still need the delay? Or are you intending to close the relay wait 1 second and then read the analog IO?

Also, more generally, you need to be thinking in terms of creating reusable VIs. In war there's a saying that "amateurs discuss tactics, professionals discuss logistics". In LV there's an analogous point to be made: "amateurs write programs, professionals write toolboxes".

For example, the digital output logic could be encapsulated into a subVI that you call twice: once to turn a bit on and once to turn it off. Also think a bit about your delay, if an error occurs do you really want to wait a second before propagating it on? Probably not. Create a subVI that wraps the built in function is a case structure controlled by an error cluster input. Now if an error occurs you can bypass the delay completely.

Also your wait is probably not doing exactly what you think it is. The version you are using waits until an internal system tick count is an exact multiple of the number to specify. This will give you a 1 second delay once the loop is running. The problem is that on the very first iteration, you don't know where the internal counter is so on that first iteration you might get a 1000 msec delay and you might get 1 msec delay.

Finally, there's no reason to have two error cluster runs passing through the producer loop. Wire the error cluster coming into the inner-most for loop to the error input of the DAQmx Create Virtual Channel VI. Now the error output of the first DAQmx Start Task VI goes to the error input of the analog read. The error output from the analog read goes to the error input of the DAQmx Stop Task VI, and finally the error output of the DAQmx Clear Task VI goes to the tunnel passing the error cluster out of the loop.

There are a few more things that you will want to do, but this will get you started.

Mike...

[JPROC]

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mikeporter wrote:

For the most part, yes. But you are only going to get one sample sent to the consumer loop after all the relays have been toggled. Move the enqueue inside the loop right next to the analog read so the consumer loop will see all the reads. Do you still need the delay? Or are you intending to close the relay wait 1 second and then read the analog IO?

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Thanks.  Yes, I'd like a bit of a delay between closing the relay and reading the ai.

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mikeporter wrote:

Also, more generally, you need to be thinking in terms of creating reusable VIs. In war there's a saying that "amateurs discuss tactics, professionals discuss logistics". In LV there's an analogous point to be made: "amateurs write programs, professionals write toolboxes".

For example, the digital output logic could be encapsulated into a subVI that you call twice: once to turn a bit on and once to turn it off. Also think a bit about your delay, if an error occurs do you really want to wait a second before propagating it on? Probably not. Create a subVI that wraps the built in function is a case structure controlled by an error cluster input. Now if an error occurs you can bypass the delay completely.

Mike...

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 I had intended on creating a subVI's from key pieces once I had everything working.

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The boolean output would alos be more efficient if you did port IO (no need to be constantly reinitializing the digital output) and define the bits in the port such that only one bit is on at a time durint the on phase and everything is off during the off phase.

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I still don't understand what the above suggestion would look like.  Can you elaborate?

[mikeporter]

That is a plan, however I find that the reduced clutter from creating the subVIs often helps me see the solution better.

Mike... 

[mikeporter]

Ok, concerning the digital output...

Doing port IO allows you to write all 8 bits of the digital port at the same time. If you write an 8-bit array that only has one bit on, it's the same as having written only that one line. The advantage is that you only have to initialize the output task one time - like you are currently doing with the analog input.

Rather than using the line selection input to alter the line that you are configuring the task to toggle, you use the input to select which bit in the array to set true.

Mike...

[JPROC]

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@mikeporter wrote:

Ok, concerning the digital output...

Doing port IO allows you to write all 8 bits of the digital port at the same time. If you write an 8-bit array that only has one bit on, it's the same as having written only that one line. The advantage is that you only have to initialize the output task one time - like you are currently doing with the analog input.

Rather than using the line selection input to alter the line that you are configuring the task to toggle, you use the input to select which bit in the array to set true.

Mike...

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I understand what your suggesting but I don't know how to implement it.

[mikeporter]

How about something like the attached. I don't know if I got your logic right, but the first time the while loop iterates, the logic toggles the first 4 bits on the port (lines 0 - 3) and the second time, it toggles the first 8 bits (lines 0 - 7).

Also, if you select the case structure around the wait function in the middle of the block diagram and then select Create SubVI from the Edit menu, you'll have your first reusable toolbox VI.

Finally, on shutdown, there is a race condition that stops the consumer loop from seeing the last data sample. Hint: if you turn on execution highlighting, the problem goes away...

Mike...

[JPROC]

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@mikeporter wrote:

How about something like the attached. I don't know if I got your logic right, but the first time the while loop iterates, the logic toggles the first 4 bits on the port (lines 0 - 3) and the second time, it toggles the first 8 bits (lines 0 - 7).

Mike...

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I like it, only problem is I'm using two NI9481's as noted in my first post which are 4 channel relay modules.  The order of operation is this:

Loop 1

Toggle Dev1/port0/lines0:3

Loop 2

Toggle Dev1/port0/lines0:3

Toggle Dev2/port0/lines0:3

The piece of this puzzle that has me struggling is how to switch from Dev1 to Dev2.

Thanks for all the help.