LabVIEW

cancel
Showing results for 
Search instead for 
Did you mean: 

Adding DRAM storage to "Finite Acquisition Multiple Channels" on FPGA

jp82,

 

I see and I am sorry for the misunderstanding. I think the easiest way to implement the clear DRAM would be to have a state at the beginning of the state machine that cleared the DRAM. Once the Data Available both go to false, the OR will be FALSE and it will go to the "Waiting for Trigger" state just you it would before. I created a new state called "Clear DRAM". I think I am passing everything through correctly to your shift registers but you might double check this. It would be helpful in future to create typedef for your state enum so you do not have to re-add in all places reference in your code after you add a case.

 

ClearDRAMState.JPG

 

Best,

 

tannerite

Tannerite
National Instruments
0 Kudos
Message 11 of 11
(219 Views)